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DESCRIPTION
The WM8980 is a low power, high quality stereo CODEC with integrated video buffer designed for portable applications such as multimedia phone, digital still camera or digital camcorder. The device integrates preamps for stereo differential mics, and includes drivers for speakers, headphone and differential or stereo line output. External component requirements are reduced as no separate microphone or headphone amplifiers are required. An integrated video buffer is provided which has programmable gain from 0-6dB (6-12dB unloaded), sync-tip clamp and a 3rd order input low pass filter for signal re-construction. Advanced on-chip digital signal processing includes a 5-band equaliser, a mixed signal Automatic Level Control for the microphone or line input through the ADC as well as a purely digital limiter function for record or playback. Additional digital filtering options are available in the ADC path, to cater for application filtering such as `wind noise reduction'. The WM8980 digital audio interface can operate as a master or a slave. An internal PLL can generate all required audio clocks for the CODEC from common reference clock frequencies, such as 12MHz and 13MHz. The WM8980 operates at analogue supply voltages from 2.5V to 3.3V, although the digital core can operate at voltages down to 1.71V to save power. The speaker outputs and OUT3/4 line outputs can run from a 5V supply if increased output power is required. Individual sections of the chip can also be powered down under software control.
WM8980
Stereo CODEC With Speaker Driver and Video Buffer
FEATURES
Stereo CODEC: * DAC SNR 98dB, THD -84dB (`A' weighted @ 48kHz) * ADC SNR 95dB, THD -80dB (`A' weighted @ 48kHz) * On-chip Headphone Driver with `capless' option - 40mW per channel into 16 / 3.3V SPKVDD * 0.9W output power into 8 BTL speaker / 5V SPKVDD - Capable of driving piezo speakers - Stereo speaker drive configuration Mic Preamps: * Stereo Differential or mono microphone Interfaces - Programmable preamp gain - Psuedo differential inputs with common mode rejection - Programmable ALC / Noise Gate in ADC path * Low-noise bias supplied for electret microphones Other Features: * Integrated video buffer with LPF filter and clamp. * Enhanced 3-D function for improved stereo separation * Digital playback limiter * 5-band Equaliser (record or playback) * Programmable ADC High Pass Filter (wind noise reduction) * Programmable ADC Notch Filter * Aux inputs for stereo analog input signals or `beep' * On-chip PLL supporting 12, 13, 19.2MHz and other clocks * Support for 8, 11.025, 12, 16, 22.05, 24, 32, 44.1 and 48kHz sample rates * Low power, low voltage - 2.5V to 3.6V (digital: 1.71V to 3.6V) * 6x6mm 40-lead QFN package
APPLICATIONS
* * Stereo Camcorder or DSC Multimedia Phone
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
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Pre-Production, March 2007, Rev 3.1
Copyright (c)2007 Wolfson Microelectronics plc.
WM8980 TABLE OF CONTENTS
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DESCRIPTION .......................................................................................................1 BLOCK DIAGRAM .................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................4 ORDERING INFORMATION ..................................................................................4 PIN DESCRIPTION ................................................................................................5 ABSOLUTE MAXIMUM RATINGS.........................................................................6 RECOMMENDED OPERATING CONDITIONS .....................................................6 ELECTRICAL CHARACTERISTICS ......................................................................7
TERMINOLOGY .......................................................................................................... 10
SPEAKER OUTPUT THD VERSUS POWER ......................................................11 POWER CONSUMPTION ....................................................................................12
ESTIMATING SUPPLY CURRENT ............................................................................. 12
AUDIO PATHS OVERVIEW .................................................................................14
SYSTEM CLOCK TIMING ........................................................................................... 15 AUDIO INTERFACE TIMING - MASTER MODE ........................................................ 15 AUDIO INTERFACE TIMING - SLAVE MODE............................................................ 16 CONTROL INTERFACE TIMING - 3-WIRE MODE .................................................... 17 CONTROL INTERFACE TIMING - 2-WIRE MODE .................................................... 18
INTERNAL POWER ON RESET CIRCUIT ..........................................................19
RECOMMENDED POWER UP/DOWN SEQUENCE .................................................. 21
DEVICE DESCRIPTION.......................................................................................25
INTRODUCTION ......................................................................................................... 25 INPUT SIGNAL PATH ................................................................................................. 27 ANALOGUE TO DIGITAL CONVERTER (ADC).......................................................... 35 INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) .......................................... 38 OUTPUT SIGNAL PATH ............................................................................................. 42 3D STEREO ENHANCEMENT .................................................................................... 49 ANALOGUE OUTPUTS............................................................................................... 49 VIDEO BUFFER .......................................................................................................... 65 DIGITAL AUDIO INTERFACES................................................................................... 69 AUDIO SAMPLE RATES ............................................................................................. 76 MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ............................................... 76 GENERAL PURPOSE INPUT/OUTPUT...................................................................... 78 OUTPUT SWITCHING (JACK DETECT)..................................................................... 79 CONTROL INTERFACE.............................................................................................. 81 RESETTING THE CHIP .............................................................................................. 82 POWER SUPPLIES .................................................................................................... 82 POWER MANAGEMENT ............................................................................................ 83
REGISTER MAP...................................................................................................84
REGISTER BITS BY ADDRESS ................................................................................. 86
DIGITAL FILTER CHARACTERISTICS .............................................................103
TERMINOLOGY ........................................................................................................ 103 DAC FILTER RESPONSES....................................................................................... 104 ADC FILTER RESPONSES....................................................................................... 104 HIGHPASS FILTER................................................................................................... 105 5-BAND EQUALISER ................................................................................................ 106
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APPLICATION INFORMATION..........................................................................110
RECOMMENDED EXTERNAL COMPONENTS ........................................................ 110
PACKAGE DIAGRAM ........................................................................................111 IMPORTANT NOTICE ........................................................................................112
ADDRESS: ................................................................................................................ 112
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WM8980 PIN CONFIGURATION
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ORDERING INFORMATION
ORDER CODE WM8980GEFL/V WM8980GEFL/RV Note: Reel quantity = 3,500 TEMPERATURE RANGE -25C to +85C -25C to +85C PACKAGE 40-lead QFN (6 x 6 mm) (Pb-free) 40-lead QFN (6 x 6 mm) (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL3 MSL3 PEAK SOLDERING TEMPERATURE 260oC 260oC
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PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NAME L2/GPIO2 RIP RIN R2/GPIO3 VBGND VBIN VBREF VBOUT VBVDD NC LRC BCLK ADCDAT DACDAT MCLK DGND DCVDD DBVDD CSB/GPIO1 SCLK SDIN MODE GPIO4 NC AUXL AUXR OUT4 OUT3 ROUT2 SPKGND LOUT2 SPKVDD VMID AGND ROUT1 LOUT1 AVDD MICBIAS LIP LIN TYPE Analogue input Analogue input Analogue input Analogue input Supply Analogue input Analogue output Analogue output Supply Not internally connected Digital Input / Output Digital Input / Output Digital Output Digital Input Digital Input Supply Supply Supply Digital Input / Output Digital Input Digital Input / Output Digital Input Digital input/output Not internally connected Analogue input Analogue input Analogue Output Analogue Output Analogue Output Supply Analogue Output Supply Reference Supply Analogue Output Analogue Output Supply Analogue Output Analogue input Analogue input Left Auxillary input Right Auxillary input Buffered midrail Headphone pseudo-ground, or Right line output or MONO mix output Buffered midrail Headphone pseudo-ground, or Left line output Second right output, or BTL speaker driver negative output Speaker ground (feeds speaker amp and OUT3/OUT4) Second left output, or BTL speaker driver positive output Speaker supply (feeds speaker amp only) Decoupling for ADC and DAC reference voltage Analogue ground (feeds ADC and DAC) Headphone or Line Output Right Headphone or Line Output Left Analogue supply (feeds ADC and DAC) Microphone Bias Left Mic Pre-amp positive input Left Mic Pre-amp negative input DAC and ADC Sample Rate Clock Digital Audio Bit Clock ADC Digital Audio Data Output DAC Digital Audio Data Input Master Clock Input Digital ground Digital core logic supply Digital buffer (I/O) supply 3-Wire Control Interface Chip Select / GPIO1 pin 3-Wire Control Interface Clock Input / 2-Wire Control Interface Clock Input 3-Wire Control Interface Data Input / 2-Wire Control Interface Data Input Control Interface Selection General purpose input/output 4 DESCRIPTION Left channel line input/secondary mic pre-amp positive input/GPIO2 pin Right Mic Pre-amp positive input Right Mic Pre-amp negative input Right channel line input/secondary mic pre-amp positive input/GPIO3 pin Video buffer ground pin Video buffer signal input Video buffer reference resistor pin Video buffer output Video buffer analogue supply
Note: It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
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WM8980 ABSOLUTE MAXIMUM RATINGS
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Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION DBVDD, DCVDD, AVDD, VBVDD supply voltages SPKVDD supply voltage Voltage range digital inputs Voltage range analogue inputs Operating temperature range, TA Storage temperature after soldering Notes 1. 2. 3. 4. 5. Analogue and digital grounds must always be within 0.3V of each other. All digital and analogue supplies are completely independent from each other. Analogue supply has to be to digital. In non-boosted mode, SPKVDD should = AVDD, if boosted SPKVDD should be 1.5x AVDD. When using PLL, DCVDD should not be 1.9V. MIN -0.3V -0.3V DGND -0.3V AGND -0.3V -25C -65C MAX +4.5V +7V DVDD +0.3V AVDD +0.3V +85C +150C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range (Core) Digital supply range (Buffer) Analogue core supply range Video buffer supply range Analogue output supply range Ground Notes 1. When using the PLL, DCVDD must not be less than 1.9V. SYMBOL DCVDD DBVDD AVDD VBVDD SPKVDD DGND,AGND, SPKGND,VBGND TEST CONDITIONS MIN 1.711 1.71 2.5 2.5 2.5 0 TYP MAX 3.6 3.6 3.6 3.6 5.5 UNIT V V V V V V
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ELECTRICAL CHARACTERISTICS
Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD=VBVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Full-scale Input Signal Level - note this changes in proportion to AVDD (Note 1) Mic PGA equivalent input noise Input resistance SYMBOL VINFS TEST CONDITIONS PGABOOST = 0dB INPPGAVOL = 0dB 0 to 20kHz Gain set to 35.25dB Gain set to 0dB Gain set to -12dB L/RIP2INPPGA = 1 MIN TYP 1.0 0 150 1.6 47 75 94 10 -12 Guaranteed monotonic 0.75 120 Boost disabled Boost enabled Gain range from AUXL/R or L/R2 input to boost/mixer Gain step size to boost/mixer Auxilliary Analogue Inputs (AUXL, AUXR) Full-scale Input Signal Level (0dB) - note this changes in proportion to AVDD Input Resistance (Note 2) VINFS AVDD/3.3 0 Left Input boost and mixer enabled, at max gain Left Input boost and mixer enabled, at 0dB gain Left Input boost and mixer enabled, at min gain Right Input boost, mixer and beep enabled, at max gain Right Input boost, mixer and beep enabled, at 0dB gain Right Input boost, mixer and beep enabled, at min gain 4.3 8.6 39.1 3 6 29 10 Vrms dBV k k k k k k pF -12 3 0 20 +6 35.25 MAX UNIT Vrms dBV uV k k k k pF dB dB dB dB dB dB dB Microphone Preamp Inputs (LIP, LIN, RIP, RIN, L2, R2)
At 35.25dB gain RMICIN RMICIN RMICIN RMICIP CMICIN
MIC Programmable Gain Amplifier (PGA) Programmable Gain Programmable Gain Step Size Mute Attenuation Selectable Input Gain Boost (0/+20dB) Gain Boost on PGA input
RAUXINLMIN RAUXINLTYP RAUXINLMAX RAUXINRMIN RAUXINRTYP RAUXINRMAX
Input Capacitance
CMICIN
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WM8980
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Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD=VBVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Automatic Level Control (ALC) Target Record Level Programmable gain Gain Hold Time (Note 3,5) Gain Ramp-Up (Decay) Time (Note 4,5) tHOLD tDCY MCLK = 12.288MHz (Note 3) ALCMODE=0 (ALC), MCLK=12.288MHz (Note 3) ALCMODE=1 (limiter), MCLK=12.288MHz (Note 3) Gain Ramp-Down (Attack) Time (Note 4,5) tATK ALCMODE=0 (ALC), MCLK=12.288MHz (Note 3) ALCMODE=1 (limiter), MCLK=12.288MHz (Note 3) Mute Attenuation Analogue to Digital Converter (ADC) Signal to Noise Ratio (Note 6) Total Harmonic Distortion (Note 7) Channel Separation (Note 9) Full-scale output SNR THD A-weighted, 0dB gain -3dBFS input 1kHz input signal PGA gains set to 0dB, OUT34BOOST=0 PGA gains set to 0dB, OUT34BOOST=1 Signal to Noise Ratio (Note 6) Total Harmonic Distortion (Note 7) Channel Separation (Note 8) Output Mixers (LMX1, RMX1) PGA gain range into mixer PGA gain step into mixer Analogue Outputs (LOUT1, ROUT1, LOUT2, ROUT2) Programmable Gain range Programmable Gain step size Mute attenuation 0dB full scale output voltage Signal to Noise Ratio Total Harmonic Distortion SNR THD A-weighted RL = 16, Po=20mW AVDD=3.3V RL = 32 , Po=20mW AVDD=3.3V Headphone Output (LOUT1, ROUT1 with 32 load) AVDD/3.3 102 0.003 -75 0.008 - 82 Vrms dB % dB % dB Monotonic 1kHz, full scale signal -57 0 1 85 +6 dB dB dB -15 0 3 +6 dB dB SNR THD A-weighted RL = 10k full-scale signal 1kHz signal 95 -84 110 AVDD/3.3 1.5x (AVDD/3.3) 98 -84 110 dB dB dB dB dB dB Vrms -22.5 -12 -1.5 35.25 ms ms dB SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
0, 2.67, 5.33, 10.67, ... , 43691 (time doubles with each step) 3.3, 6.6, 13.1, ... , 3360 (time doubles with each step) 0.73, 1.45, 2.91, ... , 744 (time doubles with each step) 0.83, 1.66, 3.33, ... , 852 (time doubles with each step) 0.18, 0.36, 0.73, ... , 186 (time doubles with each step) 120
ms
dB
Digital to Analogue Converter (DAC) to Line-Out (LOUT1, ROUT1 with 10k / 50pF load)
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Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD=VBVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Full scale output voltage, 0dB gain. (Note 9) Output Power Total Harmonic Distortion PO THD SYMBOL TEST CONDITIONS SPKBOOST=0 SPKBOOST=1 PO =200mW, RL = 8, SPKVDD=3.3V PO =320mW, RL = 8, SPKVDD=3.3V PO =500mW, RL = 8, SPKVDD=5V PO =860mW, RL = 8, SPKVDD=5V Signal to Noise Ratio SNR SPKVDD=3.3V, RL = 8 SPKVDD=5V, RL = 8 Power Supply Rejection Ratio (50Hz-22kHz) PSRR RL = 8 BTL RL = 8 BTL SPKVDD=5V (boost) OUT3BOOST=0/ OUT4BOOST=0 OUT3BOOST=1 OUT4BOOST=1 Signal to Noise Ratio (Note 6) Total Harmonic Distortion (Note7) Channel Separation (Note 8) Power Supply Rejection Ratio (50Hz-22kHz) Microphone Bias Bias Voltage Bias Current Source Output Noise Voltage Video Buffer Low pass filter order LPF -3dB cutoff LPF gain flat to within 0.1dB Maximum output voltage swing Programmable Voltage Gain Differential gain Differential phase Signal to Noise Ratio Vom Av DG DP VSNR Vin=1Vp-p Vin=1Vp-p f=100kHz, THD=1% 0 0.3 0.7 +60 3 order 10 5.3 1.25 6 MHz MHz Vp-p dB % Deg dB
rd
MIN
TYP SPKVDD/3.3 (SPKVDD/3.3)*1.5 0.04 -68 1.0 -40 0.02 -74 1.0 -40 90 90 80 69
MAX
UNIT Vrms
Speaker Output (LOUT2, ROUT2 with 8 bridge tied load, INVROUT2=1)
Output power is very closely correlated with THD; see below % dB % dB % dB % dB dB dB dB dB
OUT3/OUT4 outputs (with 10k / 50pF load) Full-scale output voltage, 0dB gain (Note 9) SPKVDD/3.3 (SPKVDD/3.3)*1.5 98 -84 100 52 56 Vrms Vrms dB dB dB dB dB
SNR THD
A-weighted RL = 10 k full-scale signal 1kHz signal RL = 10k RL = 10k SPKVDD=5V (boost)
PSRR
VMICBIAS IMICBIAS Vn
MBVSEL=0 MBVSEL=1 1K to 20kHz
0.9*AVDD 0.65*AVDD 3 15
V V mA nV/Hz
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WM8980
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Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD=VBVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Digital Input / Output Input HIGH Level Input LOW Level Output HIGH Level Output LOW Level Input capacitance Input leakage VIH VIL VOH VOL IOL=1mA IOH-1mA TBD TBD 0.9xDBVDD 0.1xDBVDD 0.7xDBVDD 0.3xDBVDD V V V V pF pA SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
TERMINOLOGY
1. 2. 3. 4. 5. 6. 7. 8. Input level to RIP and LIP is limited to a maximum of -3dB or THD+N performance will be reduced. Note when BEEP path is not enabled then AUXL and AUXR have the same input impedances. Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. It does not apply to ramping down the gain when the signal is too loud, which happens without a delay. Ramp-up and Ramp-Down times are defined as the time it takes for the PGA to sweep across 90% of its gain range. All hold, ramp-up and ramp-down times scale proportionally with MCLK Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Measured by applying a full scale signal to one channel input and measuring the level of signal apparent at the other channel output. The maximum output voltage can be limited by the speaker power supply. If OUT3BOOST, OUT4BOOST or SPKBOOST is set then SPKVDD should be 1.5xAVDD to prevent clipping taking place in the output stage (when PGA gains are set to 0dB).
9.
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SPEAKER OUTPUT THD VERSUS POWER
Speaker Power vs THD+N (8Ohm BTL Load)
AVDD=SPKVDD=DBVDD=3.3, DCVDD=1.8 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.00
THD+N (dB)
50.00
100.00
150.00
200.00
250.00
300.00
350.00
400.00
450.00
500.00
Output Power (mW)
Speaker Power vs THD+N (8Ohm BTL Load)
AVDD=DBVDD=3.3V, SPKVDD=5V, DCVDD=1.8V 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.00
THD+N (dB)
100.00
200.00
300.00
400.00
500.00
600.00
700.00
800.00
900.00
1000.00
Output Power (mW)
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WM8980 POWER CONSUMPTION
Typical current consumption for various scenarios is shown below. MODE AVDD (3.0V) (mA) 0.043 0.04 4.1 3.3 5.4 18 18 DCVDD (1.9V) (mA) 0.0008 0.0008 1.0 6.2 7.3 6.7 6.7 DBVDD1 (3.0V) (mA) <0.0001 <0.0001 0.001 0.004 0.004 0.004 0.004
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VBVDD (3.0V) (mA) 0 0 0 0 0 0 4.0
TOTAL POWER (mW) 0.12 0.12 14.1 21.1 29.4 66.1 78.1
Off Sleep (VREF maintained, no clocks) MIC Record (8kHz) 2 Stereo 16 HP Playback (48kHz, quiescent)2 Stereo 16 HP Playback (48kHz, white noise)2 Stereo 16 HP Playback (48kHz, sine wave)
2
Stereo 16 HP Playback (48kHz, sine wave) 2 video buffer enabled Table 1 Power Consumption
Notes: 1. DBVDD Current will increase with greater loading on digital I/O pins. 2. 3. 5 Band EQ is enabled. AVDD standby current will fall to nearer 15uA when thermal shutdown sensor is disabled.
ESTIMATING SUPPLY CURRENT
When either the DAC or ADC is enabled approximately 7mA will be drawn from DCVDD when DCVDD=1.8V and fs=48kHz. When the PLL is enabled approximately 1.5mA additional current will be drawn from DCVDD. The video buffer will draw approximately 4mA with no load attached. During normal operation up to 30mA will be drawn. As a general rule, digital supply currents will scale in proportion to sample rates. Supply current for analogue and digital blocks will also be lower at lower supply voltages. Power consumed by the output drivers will depend greatly on the signal characteristics. A quiet signal, or a signal with long periods of silence will consume less power than a signal which is continuously loud.
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Estimated supply current for the analogue blocks is shown in Table 2. Note that power dissipated in the load is not shown. REGISTER BIT BUFDCOPEN OUT4MIXEN OUT3MIXEN PLLEN MICBEN BIASEN BUFIOEN VMIDSEL ROUT1EN LOUT1EN BOOSTENR BOOSTENL INPPGAENR INPPGAENL ADCENR ADCENL OUT4EN OUT3EN LOUT2EN ROUT2EN RMIXEN LMIXEN DACENR DACENL 0.1 0.2 0.2 1.2 (with clocks applied) 0.5 0.3 0.1 0.3 (5k VMID) <0.1 (75k or 300k VMID) 0.4 0.4 0.2 0.2 0.2 0.2 2.6 (x64, ADCOSR=0) 4.9 ( x128, ADCOSR=1) 2.6 (x64, ADCOSR=0) 4.9 ( x128, ADCOSR=1) 0.2 0.2 1mA from SPKVDD + 0.2mA from AVDD in 5V mode 1mA from SPKVDD + 0.2mA from AVDD in 5V mode 0.2 0.2 1.8 (x64, DACOSR=0) 1.9 (x128, DACOSR=1) 1.8 (x64, DACOSR=0) 1.9 (x128, DACOSR=1) AVDD CURRENT (mA) AVDD=3.3V
Table 2 AVDD Supply Current (AVDD=3.3V)
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WM8980 AUDIO PATHS OVERVIEW
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SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL MCLK tMCLKH tMCLKY
Figure 1 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25oC PARAMETER System Clock Timing Information MCLK cycle time MCLK duty cycle Note 1: PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz. TMCLKY TMCLKDS MCLK=SYSCLK (=256fs) MCLK input to PLL Note 1 81.38 20 40:60 60:40 ns ns SYMBOL CONDITIONS MIN TYP MAX UNIT
AUDIO INTERFACE TIMING - MASTER MODE
7
Figure 2 Digital Audio Data Timing - Master Mode (see Control Interface)
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WM8980
Test Conditions
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DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information LRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge DACDAT hold time from BCLK rising edge tDL tDDA tDST tDHT 10 10 10 10 ns ns ns ns SYMBOL MIN TYP MAX UNIT
AUDIO INTERFACE TIMING - SLAVE MODE
Figure 3 Digital Audio Data Timing - Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK= 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information BCLK cycle time BCLK pulse width high BCLK pulse width low LRC set-up time to BCLK rising edge LRC hold time from BCLK rising edge DACDAT hold time from BCLK rising edge ADCDAT propagation delay from BCLK falling edge Note: BCLK period should always be greater than or equal to MCLK period. tBCY tBCH tBCL tLRSU tLRH tDH tDD 50 20 20 10 10 10 10 ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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CONTROL INTERFACE TIMING - 3-WIRE MODE
Figure 4 Control Interface Timing - 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, TA=+25 C, Slave Mode, fs=48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SCLK to SDIN hold time CSB pulse width low CSB pulse width high CSB rising to SCLK rising Pulse width of spikes that will be suppressed tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS tps 80 200 80 80 40 40 40 40 40 0 5 ns ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8980
CONTROL INTERFACE TIMING - 2-WIRE MODE
t3 SDIN t4 t6 SCLK t1 t9 t7 t2 t5 t3
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Figure 5 Control Interface Timing - 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width of spikes that will be suppressed t1 t2 t3 t4 t5 t6 t7 t8 t9 tps 0 600 900 5 0 1.3 600 600 600 100 300 300 526 kHz us ns ns ns ns ns ns ns ns ns SYMBOL TA=+25oC, MIN Slave TYP Mode, MAX fs=48kHz, UNIT
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INTERNAL POWER ON RESET CIRCUIT
Figure 6 Internal Power on Reset Circuit Schematic The WM8980 includes an internal Power-On-Reset Circuit, as shown in Figure 6, which is used reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and monitors DVDD. It asserts PORB low if AVDD or DVDD is below a minimum threshold.
Figure 7 Typical Power up Sequence where AVDD is Powered before DVDD Figure 7 shows a typical power-up sequence where AVDD comes up first. When AVDD goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Now AVDD is at full supply level. Next DVDD rises to Vpord_on and PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where AVDD falls first, PORB is asserted low whenever AVDD drops below the minimum threshold Vpora_off.
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Figure 8 Typical Power up Sequence where DVDD is Powered before AVDD Figure 8 shows a typical power-up sequence where DVDD comes up first. First it is assumed that DVDD is already up to specified operating voltage. When AVDD goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD rises to Vpora_on, PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where DVDD falls first, PORB is asserted low whenever DVDD drops below the minimum threshold Vpord_off.
SYMBOL Vpora Vpora_on Vpora_off Vpord_on Vpord_off
MIN 0.4 0.9 0.4 0.5 0.4
TYP 0.6 1.2 0.6 0.7 0.6
MAX 0.8 1.6 0.8 0.9 0.8
UNIT V V V V V
Table 3 Typical POR operation (typical values, not tested) Notes: 1. If AVDD and DVDD suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go below Vpora_off or Vpord_off) then the chip will not reset and will resume normal operation when the voltage is back to the recommended level again. The chip will enter reset at power down when AVDD or DVDD falls below Vpora_off or Vpord_off. This may be important if the supply is turned on and off frequently by a power management system. The minimum tpor period is maintained even if DVDD and AVDD have zero rise time. This specification is guaranteed by design rather than test.
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In order to minimise output pop and click noise, it is recommended that the WM8980 device is powered up and down using one of the following sequences: Power-up when NOT using the output 1.5x boost stage: 1. 2. 3. 4. 5. 6. 7. 8. 9. Turn on external power supplies. Wait for supply voltage to settle. Mute all analogue outputs. Set L/RMIXEN = 1 and DACENL/R = 1 in register R3. Set BUFIOEN = 1 and VMIDSEL[1:0] to required value in register R1. Wait for the VMID supply to settle. *Refer notes 1 and 2. Set BIASEN = 1 in register R1. Set L/ROUT1EN = 1 in register R2. Enable other mixers as required. Enable other outputs as required. Set remaining registers.
RECOMMENDED POWER UP/DOWN SEQUENCE
Power-up when using the output 1.5x boost stage: 1. 2. 3. 4. 5. 6. 7. 8. 9. Turn on external power supplies. Wait for supply voltage to settle. Mute all analogue outputs. Enable unused output chosen from L/ROUT2, OUT3 or OUT4. If unused output not available, chose one of these outputs not required at power up. Set BUFDCOPEN = 1 and BUFIOEN = 1 in register R1. Set SPKBOOST = 1 in register R49. Set VMIDSEL[1:0] to required value in register R1. Wait for the VMID supply to settle. *Refer notes 1 and 2. Set L/RMIXEN = 1 and DACENL/R = 1 in register R3. Set BIASEN = 1 in register R1. Set L/ROUT2EN = 1 in register R3. *Note 3.
10. Enable other mixers as required. 11. Enable other outputs as required. 12. Set remaining registers.
Power Down (all cases): 1. 2. 3. 4. 5. Mute all analogue outputs. Disable Power Management Register 1. R1 = 0x00. Disable Power Management Register 2. R2 = 0x00. Disable Power Management Register 3. R3 = 0x00. Remove external power supplies.
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Notes: 1.
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This step enables the internal device bias buffer and the VMID buffer for unassigned inputs/outputs. This will provide a startup reference voltage for all inputs and outputs. This will cause the inputs and outputs to ramp towards VMID (NOT using output 1.5x boost) or 1.5 x (AVDD/2) (using output 1.5x boost) in a way that is controlled and predictable (see note 2). Choose the value of the VMIDSEL bits based on the startup time (VMIDSEL=10 for slowest startup, VMIDSEL=11 for fastest startup). Startup time is defined by the value of the VMIDSEL bits (the reference impedance) and the external decoupling capacitor on VMID. Setting DACEN to off while operating in x1.5 boost mode will cause the VMID voltage to drop to AVDD/2 midrail level and cause an output pop.
2.
3.
In addition to the power on sequence, it is recommended that the zero cross functions are used when changing the volume in the PGAs to avoid any audible pops or clicks.
Vpor_on Vpora
Power Supply
DGND
Vpor_off
POR
No Power POR Undefined POR
Device Ready Internal POR active DNC
I2S Clocks
DNC
ADC Internal State
tadcint
Power down Init Normal Operation PD Init
tadcint
Normal Operation Power down
tmidrail_on
(Note 1)
tmidrail_off
(Note 2)
Analogue Inputs ADCDAT pin
(Note 3)
AVDD/2 GD GD GD GD
ADCEN bit INPPGAEN bit VMIDSEL/ BIASEN bits
ADC enabled
ADC off
ADC enabled
INPPGA enabled
(Note 4)
VMID enabled
Figure 9 ADC Power Up and Down Sequence (not to scale)
SYMBOL tmidrail_on tmidrail_off tadcint ADC Group Delay
MIN
TYPICAL 500 >10 2/fs 29/fs
MAX
UNIT ms s n/fs n/fs
Table 4 Typical POR Operation (typical values, not tested)
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The analogue input pin charge time, tmidrail_on, is determined by the VMID pin charge time. This time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. The analogue input pin discharge time, tmidrail_off, is determined by the analogue input coupling capacitor discharge time. The time, tmidrail_off, is measured using a 1F capacitor on the analogue input but will vary dependent upon the value of input coupling capacitor. While the ADC is enabled there will be LSB data bit activity on the ADCDAT pin due to system noise but no significant digital output will be present. The VMIDSEL and BIASEN bits must be set to enable analogue input midrail voltage and for normal ADC operation. ADCDAT data output delay from power up - with power supplies starting from 0V - is determined primarily by the VMID charge time. ADC initialisation and power management bits may be set immediately after POR is released; VMID charge time will be significantly longer and will dictate when the device is stabilised for analogue input. ADCDAT data output delay at power up from device standby (power supplies already applied) is determined by ADC initialisation time, 2/fs.
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3. 4. 5.
6.
Figure 10 DAC Power Up and Down Sequence (not to scale)
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SYMBOL tline_midrail_on tline_midrail_off thp_midrail_on thp__midrail_off tdacint DAC Group Delay MIN TYPICAL 500 1 500 6 2/fs 29/fs MAX UNIT ms s ms s n/fs n/fs
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Table 5 Typical POR Operation (typical values, not tested) Notes: 1. The lineout charge time, tline_midrail_on, is mainly determined by the VMID pin charge time. This time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. The values above were measured using a 4.7F capacitor. It is not advisable to allow DACDAT data input during initialisation of the DAC. If the DAC data value is not zero at point of initialisation, then this is likely to cause a pop noise on the analogue outputs. The same is also true if the DACDAT is removed at a non-zero value, and no mute function has been applied to the signal beforehand. The lineout discharge time, tline_midrail_off, is dependent upon the value of the lineout coupling capacitor and the leakage resistance path to ground. The values above were measured using a 10F output capacitor. The headphone charge time, thp_midrail_on, is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. The values above were measured using a 4.7F VMID decoupling capacitor. The headphone discharge time, thp_midrail_off, is dependent upon the value of the headphone coupling capacitor and the leakage resistance path to ground. The values above were measured using a 100F capacitor. The VMIDSEL and BIASEN bits must be set to enable analogue output midrail voltage and for normal DAC operation.
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DEVICE DESCRIPTION
INTRODUCTION
The WM8980 is a low power audio codec combining a high quality stereo audio DAC and ADC, with flexible line and microphone input and output processing. Applications for this device include multimedia phones, stereo digital camcorders, and digital still cameras with either mono or stereo, audio and video, record and playback capability. The integrated video buffer makes the device suitable for driving both audio and video signals directly to a television or VCR.
FEATURES
The chip offers great flexibility in use, and so can support many different modes of operation as follows:
MICROPHONE INPUTS
Two pairs of stereo microphone inputs are provided, allowing a pair of stereo microphones to be pseudo-differentially connected, with user defined gain using internal resistors. The provision of the common mode input pin for each stereo input allows for rejection of common mode noise on the microphone inputs (level depends on gain setting chosen). A microphone bias is output from the chip which can be used to bias both microphones. The signal routing can be configured to allow manual adjustment of mic levels, or to allow the ALC loop to control the level of mic signal that is transmitted. Total gain through the microphone paths of up to +55.25dB can be selected.
PGA AND ALC OPERATION
A programmable gain amplifier is provided in the input path to the ADC. This may be used manually or in conjunction with a mixed analogue/digital automatic level control (ALC) which keeps the recording volume constant.
LINE INPUTS (AUXL, AUXR)
The inputs, AUXL and AUXR, can be used as a stereo line input or as an input for warning tones (or `beeps') etc. These inputs can be summed into the record paths, along with the microphone preamp outputs, so allowing for mixing of audio with `backing music' etc as required.
ADC
The stereo ADC uses a 24-bit delta sigma oversampling architecture to deliver optimum performance with low power consumption.
HI-FI DAC
The hi-fi DAC provides high quality audio playback suitable for all portable audio hi-fi type applications, including MP3 players and portable disc players of all types.
OUTPUT MIXERS
Flexible mixing is provided on the outputs of the device. A stereo mixer is provided for the stereo headphone or line outputs, LOUT1/ROUT1, and additional summers on the OUT3/OUT4 outputs allow for an optional differential or stereo line output on these pins. Gain adjustment PGAs are provided for the LOUT1/ROUT1 and LOUT2/ROUT2 outputs, and signal switching is provided to allow for all possible signal combinations. The output buffers can be configured in several ways, allowing support of up to three sets of external transducers; ie stereo headphone, BTL speaker, and BTL earpiece may be connected simultaneously. Thermal implications should be considered before simultaneous full power operation of all outputs is attempted. Alternatively, if a speaker output is not required, the LOUT2 and ROUT2 pins might be used as a stereo headphone driver, (disable output invert buffer on ROUT2). In that case two sets of headphones might be driven, or the LOUT2 and ROUT2 pins used as a line output driver.
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Pre-Production OUT3 and OUT4 can be configured to provide an additional stereo lineout from the output of the DACs, the mixers or the input microphone boost stages. Alternatively OUT4 can be configured as a mono mix of left and right DACs or mixers, or simply a buffered version of the chip midrail reference voltage. OUT3 can also be configured as a buffered VMID output. This voltage may then be used as a headphone `pseudo ground' allowing removal of the large AC coupling capacitors often used in the output path.
AUDIO INTERFACES
The WM8980 has a standard audio interface, to support the transmission of stereo data to and from the chip. This interface is a 3 wire standard audio interface which supports a number of audio data formats including I2S, DSP/PCM Mode (a burst mode in which LRC sync plus 2 data packed words are transmitted), MSB-First, left justified and MSB-First, right justified, and can operate in master or slave modes.
CONTROL INTERFACES
To allow full software control over all features, the WM8980 offers a choice of 2 or 3 wire control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. Selection between the modes is via the MODE pin. In 2 wire mode the address of the device is fixed as 0011010.
CLOCKING SCHEMES
WM8980 offers the normal audio DAC clocking scheme operation, where 256fs MCLK is provided to the DAC and ADC. A PLL is included which may be used to generate these clocks in the event that they are not available from the system controller. This PLL uses an input clock, typically the 12MHz USB or ilink clock, to generate high quality audio clocks. If this PLL is not required for generation of these clocks, it can be reconfigured to generate alternative clocks which may then be output on the GPIO pins and used elsewhere in the system.
VIDEO BUFFER
The WM8980 incorporates a current mode output video buffer with an input 3rd order Low Pass Filter (LPF) and clamp. The gain through this buffer can be programmed as 0dB or 6dB via the control interface. The current mode output means that the signal swing seen at the output of the buffer will be the same as that at the connection to the receiving equipment (e.g. a TV). Note that the input to the receiver should be AC coupled and terminated to 75, as is standard, for best performance.
POWER CONTROL
The design of the WM8980 has given much attention to power consumption without compromising performance. It operates at very low voltages, and includes the ability to power off any unused parts of the circuitry under software control, and includes standby and power off modes.
OPERATION SCENARIOS
Flexibility in the design of the WM8980 allows for a wide range of operational scenarios, some of which are proposed below: Multimedia phone; High quality playback to a stereo headset, a mono ear speaker or a loudspeaker is supported, allowing Hi-Fi playback to be mixed with voice and other analogue inputs while simultaneously transmitting a differential output from the microphone amplifier. A 5-band EQ enables Hi-Fi playback to be customised to suit the user's preferences and the music style, while programmable filtering allows fixed-frequency noise (e.g. 217Hz) to be reduced in the digital domain. Video playback directly to TV is supported using the integrated video buffer.
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Stereo Camcorder; The provision of two stereo microphone preamplifiers, allows support for both internal and external microphones. All drivers for speaker, headphone and line output connections are integrated. The selectable `application filters' after the ADC provide for features such as `wind noise' reduction, or mechanical noise reducing filters. The integrated video buffer allows direct connection to a TV or VCR for both video and audio (via line outputs). Stereo Digital still camera recording; Support for digital stereo video with audio recording is similar to the camcorder case. But additionally if the DSC supports MP3 playback, and perhaps recording, the ability of the ADCs to support full 48ks/s high quality stereo recording increases device flexibility. The integrated video buffer allows direct connection to the TV for display of moving and still images. Mono Digital still camera; Full control over device functionality, and power control is provided, allowing for the case of mono DSC recording, when half of the ADC and mic and line functionality may be disabled to save power. In the mono case, the single ADC channel of audio data is sent out over both Left and Right channels of the audio interface when normal I2S type interface format is used. In the case where DSP mode is used, and mono data is being sent, only the signal channel of mono data is sent. The integrated video buffer allows direct connection to the TV for display of moving and still images.
AUXILIARY ANALOGUE INPUTS
An analogue stereo FM tuner or other auxiliary analogue input can be connected to the Line inputs of WM8980, and the stereo signal listened to via headphones, or recorded, simultaneously if required.
INPUT SIGNAL PATH
The WM8980 has a number of flexible analogue inputs. There are two input channels, Left and Right, each of which consists of an input PGA stage followed by a boost/mix stage which drives into the hi-fi ADC. Each input path has three input pins which can be configured in a variety of ways to accommodate single-ended, differential or dual differential microphones. There are two auxiliary input pins which can be fed into to the input boost/mix stage as well as driving into the output path. A bypass path exists from the output of the boost/mix stage into the output left/right mixers.
MICROPHONE INPUTS
The WM8980 can accommodate a variety of microphone configurations including single ended and differential inputs. The inputs to the left differential input PGA are LIN, LIP and L2. The inputs to the right differential input PGA are RIN, RIP and R2. In single-ended microphone input configuration the microphone signal should be input to LIN or RIN and the internal NOR gate configured to clamp the non-inverting input of the input PGA to VMID. In differential mode the larger signal should be input to LIP or RIP and the smaller (e.g. noisy ground connection) should be input to LIN or RIN.
Figure 11 Microphone Input PGA Circuit
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The input PGAs are enabled by the IPPGAENL/R register bits. REGISTER ADDRESS R2 Power Management 2 2 BIT LABEL INPPGAENL DEFAULT 0
Pre-Production
DESCRIPTION Left channel input PGA enable 0 = disabled 1 = enabled Right channel input PGA enable 0 = disabled 1 = enabled
3
INPPGAENR
0
Table 6 Input PGA Enable Register Settings
REGISTER ADDRESS R44 Input Control
BIT 0
LABEL LIP2INPPGA
DEFAULT 1
DESCRIPTION Connect LIP pin to left channel input PGA amplifier positive terminal. 0 = LIP not connected to input PGA 1 = input PGA amplifier positive terminal connected to LIP (constant input impedance) Connect LIN pin to left channel input PGA negative terminal. 0=LIN not connected to input PGA 1=LIN connected to input PGA amplifier negative terminal. Connect L2 pin to left channel input PGA positive terminal. 0=L2 not connected to input PGA 1=L2 connected to input PGA amplifier positive terminal (constant input impedance). Connect RIP pin to right channel input PGA amplifier positive terminal. 0 = RIP not connected to input PGA 1 = right channel input PGA amplifier positive terminal connected to RIP (constant input impedance) Connect RIN pin to right channel input PGA negative terminal. 0=RIN not connected to input PGA 1=RIN connected to right channel input PGA amplifier negative terminal. Connect R2 pin to right channel input PGA positive terminal. 0=R2 not connected to input PGA 1=R2 connected to input PGA amplifier positive terminal (constant input impedance).
1
LIN2INPPGA
1
2
L2_2INPPGA
0
4
RIP2INPPGA
1
5
RIN2INPPGA
1
6
R2_2INPPGA
0
Table 7 Input PGA Control
INPUT PGA VOLUME CONTROLS
The input microphone PGAs have a gain range from -12dB to +35.25dB in 0.75dB steps. The gain from the LIN/RIN input to the PGA output and from the L2/R2 amplifier to the PGA output are always common and controlled by the register bits INPPGAVOLL/R[5:0]. These register bits also affect the LIP pin when LIP2INPPGA=1, the L2 pin when L2_2INPPGA=1, the RIP pin when RIP2INPPGA=1 and the L2 pin when L2_2INPPGA=1. When the Automatic Level Control (ALC) is enabled the input PGA gains are controlled automatically and the INPPGAVOLL/R bits should not be used.
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REGISTER ADDRESS R45 Left channel input PGA volume control BIT 5:0 LABEL INPPGAVOLL DEFAULT 010000 DESCRIPTION Left channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = 35.25dB Mute control for left channel input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Left channel input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. INPPGAVOLL and INPPGAVOLR volume do not update until a 1 is written to INPPGAUPDATE (in reg 45 or 46) Right channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = +35.25dB Mute control for right channel input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Right channel input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. INPPGAVOLL and INPPGAVOLR volume do not update until a 1 is written to INPPGAUPDATE (in reg 45 or 46) ALC function select: 00=ALC off 01=ALC right only 10=ALC left only 11=ALC both on
6
INPPGAMUTEL
0
7
INPPGAZCL
0
8
INPPGAUPDATE
Not latched 010000
R46 Right channel input PGA volume control
5:0
INPPGAVOLR
6
INPPGAMUTER
0
7
INPPGAZCR
0
8
INPPGAUPDATE
Not latched 00
R32 ALC control 1
8:7
ALCSEL
Table 8 Input PGA Volume Control
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VOLUME UPDATES
Pre-Production
Volume settings will not be applied to the PGAs until a '1' is written to one of the INPPGAUPDATE bits. This is to allow left and right channels to be updated at the same time, as shown in Figure 12.
Figure 12 Simultaneous Left and Right Volume Updates If the volume is adjusted while the signal is a non-zero value, an audible click can occur as shown in Figure 13.
Figure 13 Click Noise During Volume Update In order to prevent this click noise, a zero cross function is provided. When enabled, this will cause the PGA volume to update only when a zero crossing occurs, minimising click noise as shown in Figure 14.
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Figure 14 Volume Update Using Zero Cross Detection If there is a long period where no zero-crossing occurs, a timeout circuit in the WM8980 will automatically update the volume. The volume updates will occur between one and two timeout periods, depending on when the INPPGAUPDATE bit is set as shown in Figure 15.
Figure 15 Volume Update after Timeout
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AUXILLIARY INPUTS
Pre-Production
There are two auxilliary inputs, AUXL and AUXR which can be used for a variety of purposes such as stereo line inputs or as a `beep' input signal to be mixed with the outputs. The AUXL/R inputs can be used as a line input to the input BOOST stage which has gain adjust of 12dB to +6dB in 3dB steps (plus off). See the INPUT BOOST section for further details. The AUXL/R inputs can also be mixed into the output channel mixers, with a gain of -15dB to +6dB plus off. In addition the AUXR input can be summed into the Right speaker output path (ROUT2) with a gain adjust of -15 to +6dB. This allows a `beep' input to be output on the speaker outputs only without affecting the headphone or lineout signals.
INPUT BOOST
Each of the stereo input PGA stages is followed by an input BOOST circuit. The input BOOST circuit has 3 selectable inputs: the input microphone PGA output, the AUX amplifier output and the L2/R2 input pin (can be used as a line input, bypassing the input PGA). These three inputs can be mixed together and have individual gain boost/adjust as shown in Figure 16.
Figure 16 Input Boost Stage The input PGA paths can have a +20dB boost (PGABOOSTL/R=1) , a 0dB pass through (PGABOOSTL/R=0) or be completely isolated from the input boost circuit (INPPGAMUTEL/R=1).
REGISTER ADDRESS R47 Left Input BOOST control
BIT 8
LABEL PGABOOSTL
DEFAULT 1
DESCRIPTION Boost enable for left channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Boost enable for right channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage.
R48 Right Input BOOST control
8
PGABOOSTR
1
Table 9 Input BOOST Stage Control
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The Auxilliary amplifier path to the BOOST stages is controlled by the AUXL2BOOSTVOL[2:0] and AUXR2BOOSTVOL[2:0] register bits. When AUXL2BOOSTVOL/AUXR2BOOSTVOL=000 this path is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB. The L2/R2 path to the BOOST stage is controlled by the LIP2BOOSTVOL[2:0] and the RIP2BOOSTVOL[2:0] register bits. When L2_2BOOSTVOL/R2_2BOOSTVOL=000 the L2/R2 input pin is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB.
REGISTER ADDRESS R47 Left channel Input BOOST control
BIT 2:0
LABEL AUXL2BOOSTVOL
DEFAULT 000
DESCRIPTION Controls the auxilliary amplifer to the left channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Controls the L2 pin to the left channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Controls the auxilliary amplifer to the right channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Controls the R2 pin to the right channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage
6:4
L2_2BOOSTVOL
000
R48 Right channel Input BOOST control
2:0
AUXR2BOOSTVOL
000
6:4
R2_2BOOSTVOL
000
Table 10 Input BOOST Stage Control
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The BOOST stage is enabled under control of the BOOSTEN register bit. REGISTER ADDRESS R2 Power management 2 BIT 4 LABEL BOOSTENL DEFAULT 0
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DESCRIPTION Left channel Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON Right channel Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON
5
BOOSTENR
0
Table 11 Input BOOST Enable Control
MICROPHONE BIASING CIRCUIT
The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can be altered via the MBVSEL register bit. When MBVSEL=0, MICBIAS=0.9*AVDD and when MBVSEL=1, MICBIAS=0.65*AVDD. The output can be enabled or disabled using the MICBEN control bit. REGISTER ADDRESS R1 Power management 1 BIT 4 LABEL MICBEN DEFAULT 0 DESCRIPTION Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON
Table 12 Microphone Bias Enable Control REGISTER ADDRESS R44 Input control BIT 8 LABEL MBVSEL DEFAULT 0 DESCRIPTION Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.65 * AVDD
Table 13 Microphone Bias Voltage Control The internal MICBIAS circuitry is shown in Figure 17. Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit the MICBIAS current to 3mA.
Figure 17 Microphone Bias Schematic
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The WM8980 uses stereo multi-bit, oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1.0Vrms. Any voltage greater than full scale may overload the ADC and cause distortion.
ANALOGUE TO DIGITAL CONVERTER (ADC)
ADC DIGITAL FILTERS
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital filter path for each ADC channel is illustrated in Figure 18.
Figure 18 ADC Digital Filter Path The ADCs are enabled by the ADCENL/R register bit. REGISTER ADDRESS R2 Power management 2 BIT 0 LABEL ADCENL DEFAULT 0 DESCRIPTION Enable ADC left channel: 0 = ADC disabled 1 = ADC enabled Enable ADC right channel: 0 = ADC disabled 1 = ADC enabled
1
ADCENR
0
Table 14 ADC Enable Control The polarity of the output signal can also be changed under software control using the ADCLPOL/ADCRPOL register bit. The oversampling rate of the ADC can be adjusted using the ADCOSR register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when ADCOSR=1 the oversample rate is 128x which gives best performance. REGISTER ADDRESS R14 ADC Control BIT 0 LABEL ADCLPOL DEFAULT 0 DESCRIPTION ADC left channel polarity adjust: 0=normal 1=inverted ADC right channel polarity adjust: 0=normal 1=inverted ADC oversample rate select: 0=64x (lower power) 1=128x (best performance)
1
ADCRPOL
0
3
ADCOSR
0
Table 15 ADC Control
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SELECTABLE HIGH PASS FILTER
Pre-Production
A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown in Table 17.
REGISTER ADDRESS R14 ADC Control 8
BIT
LABEL HPFEN
DEFAULT 1
DESCRIPTION High Pass Filter Enable 0=disabled 1=enabled Select audio mode or application mode 0=Audio mode (1st order, fc = ~3.7Hz) 1=Application mode (2nd order, fc = HPFCUT) Application mode cut-off frequency See Table 17 for details.
7
HPFAPP
0
6:4
HPFCUT
000
Table 16 ADC Enable Control
HPFCUT [2:0] 8 000 001 010 011 100 101 110 111 82 102 131 163 204 261 327 408
SR=101/100 11.025 113 141 180 225 281 360 450 563 12 122 153 156 245 306 392 490 612 16 82 102 131 163 204 261 327 408
SR=011/010 fs (kHz) 22.05 113 141 180 225 281 360 450 563 24 122 153 156 245 306 392 490 612 32 82 102 131 163 204 261 327 408
SR=001/000 44.1 113 141 180 225 281 360 450 563 48 122 153 156 245 306 392 490 612
Table 17 High Pass Filter Cut-off Frequencies (HPFAPP=1). Values in Hz. Note that the High Pass filter values (when HPFAPP=1) are calculated with the assumption that the SR register bits are set correctly for the actual sample rate as shown in Table 17.
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PROGRAMMABLE NOTCH FILTER
A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup there is an NFU (Notch Filter Update) flag which should be set only when all four registers are setup. REGISTER ADDRESS R27 Notch Filter 1 7 BIT 6:0 LABEL NFA0[13:7] NFEN DEFAULT 0 0 DESCRIPTION Notch Filter a0 coefficient, bits [13:7] Notch filter enable: 0=Disabled 1=Enabled 8 NFU 0 Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. R28 Notch Filter 2 6:0 8 NFA0[6:0] NFU 0 0 Notch Filter a0 coefficient, bits [6:0] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. R29 Notch Filter 3 6:0 8 NFA1[13:7] NFU 0 0 Notch Filter a1 coefficient, bits [13:7] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. R30 Notch Filter 4 0-6 8 NFA1[6:0] NFU 0 0 Notch Filter a1 coefficient, bits [6:0] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Table 18 Notch Filter Function The coefficients are calculated as follows:
a0 =
1 - tan( wb / 2) 1 + tan( wb / 2)
a1 = -(1 + a0 ) cos(w0 )
Where:
w0 = 2f c / f s
wb = 2f b / f s
fc = centre frequency in Hz, fb = -3dB bandwidth in Hz, fs = sample frequency in Hz The actual register values can be determined from the coefficients as follows: NFA0 = -a0 x 213 NFA1 = -a1 x 212
DIGITAL ADC VOLUME CONTROL
The output of the ADCs can be digitally attenuated over a range from -127dB to 0dB in 0.5dB steps. The gain for a given eight-bit code X is given by: 0.5 x (G-255) dB for 1 G 255; MUTE for G = 0
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REGISTER ADDRESS R15 Left channel ADC Digital Volume BIT 7:0 LABEL ADCVOLL [7:0] DEFAULT 11111111 ( 0dB ) DESCRIPTION
Pre-Production
Left ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB ADC left and ADC right volume do not update until a 1 is written to ADCVU (in reg 15 or 16) Right ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB ADC left and ADC right volume do not update until a 1 is written to ADCVU (in reg 15 or 16)
8
ADCVU
Not latched 11111111 ( 0dB )
R16 Right channel ADC Digital Volume
7:0
ADCVOLR [7:0]
8
ADCVU
Not latched
Table 19 ADC Digital Volume Control
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC)
The WM8980 has an automatic PGA gain control circuit, which can function as an input peak limiter or as an automatic level control (ALC). In input peak limiter mode (ALCMODE bit = 1), a digital peak detector detects when the input signal goes above a predefined level and will ramp the PGA gain down to prevent the signal becoming too large for the input range of the ADC. When the signal returns to a level below the threshold, the PGA gain is slowly returned to its starting level. The peak limiter cannot increase the PGA gain above its static level.
Figure 19 Input Peak Limiter Operation
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In ALC mode (ALCMODE bit = 0) the circuit aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary.
Figure 20 ALC Operation The ALC/Limiter function is enabled by setting the register bit ALCSEL. When enabled, the recording volume can be programmed between -6dB and -28.5dB (relative to ADC full scale) using the ALCLVL register bits. An upper limit for the PGA gain can be imposed by setting the ALCMAXGAIN control bits and a lower limit for the PGA gain can be imposed by setting the ALCMINGAIN control bits. ALCHLD, ALCDCY and ALCATK control the hold, decay and attack times, respectively: Hold time is the time delay between the peak level detected being below target and the PGA gain beginning to ramp up. It can be programmed in power-of-two (2n) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. up to 43.7s. Alternatively, the hold time can also be set to zero. The hold time is not active in limiter mode (ALCMODE = 1). The hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. Decay (Gain Ramp-Up) Time is the time that it takes for the PGA gain to ramp up and is given as a time per gain step, time per 6dB change and time to ramp up over 90% of it's range. The decay time can be programmed in power-of-two (2n) steps, from 3.3ms/6dB, 6.6ms/6dB, 13.1ms/6dB, etc. to 3.36s/6dB. Attack (Gain Ramp-Down) Time is the time that it takes for the PGA gain to ramp down and is given as a time per gain step, time per 6dB change and time to ramp down over 90% of it's range. The attack time can be programmed in power-of-two (2n) steps, from 832us/6dB, 1.66ms/6dB, 3.328us/6dB, etc. to 852ms/6dB. NB, In peak limiter mode the gain control circuit runs approximately 4x faster to allow reduction of fast peaks. Attack and Decay times for peak limiter mode are given below.
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Pre-Production The hold, decay and attack times given in Table 20 are constant across sample rates so long as the SR bits are set correctly. E.g. when sampling at 48kHz the sample rates stated in Table 20 will only be correct if the SR bits are set to 000 (48kHz). If the actual sample rate was only 44.1kHz then the hold, decay and attack times would be scaled down by 44.1/48.
REGISTER ADDRESS R32 ALC Control 1
BIT 8:7
LABEL ALCSEL
DEFAULT 00
DESCRIPTION ALC function select: 00=ALC off 01=ALC right only 10=ALC left only 11=ALC both on Set Maximum Gain of PGA 111=+35.25dB 110=+29.25dB 101=+23.25dB 100=+17.25dB 011=+11.25dB 010=+5.25dB 001=-0.75dB 000=-6.75dB Set minimum gain of PGA 000=-12dB 001=-6dB 010=0dB 011=+6dB 100=+12dB 101=+18dB 110=+24dB 111=+30dB ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ... (time doubles with every step) 1111 = 43.691s ALC target - sets signal level at ADC input 1111 : -1.5dBFS 1110 : -1.5dBFS 1101 : -3dBFS 1100 : -4.5dBFS ...... (-1.5dB steps) 0001 : -21dBFS 0000 : -22.5dBFS
5:3
ALCMAXGAIN [2:0]
111 (+35.25dB)
2:0
ALCMINGAIN [2:0]
000 (-12dB)
R33 ALC Control 2
7:4
ALCHLD [3:0]
0000 (0ms)
3:0
ALCLVL [3:0]
1011 (-6dB)
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WM8980
Determines the ALC mode of operation: 0=ALC mode 1=Limiter mode Decay (gain ramp-up) time (ALCMODE ==0) Per step 0000 0001 0010 1010 or higher 0011 (2.9ms/6dB) 410us 820us 1.64ms 420ms Per 6dB 3.3ms 6.6ms 13.1ms 3.36s 90% of range 24ms 48ms 192ms 24.576s
7:4
ALCDCY [3:0]
0011 (13ms/6dB)
... (time doubles with every step)
Decay (gain ramp-up) time (ALCMODE ==1) Per step 0000 0001 0010 1010 90.8us 181.6us 363.2us 93ms Per 6dB 726.4us 1.453ms 2.905ms 744ms 90% of range 5.26ms 10.53ms 21.06ms 5.39s
... (time doubles with every step) 3:0 ALCATK [3:0] 0010 (832us/6dB) ALC attack (gain ramp-down) time (ALCMODE == 0) Per step 0000 0001 0010 1010 or higher 0010 (182us/6dB) 104us 208us 416us 106ms Per 6dB 832us 1.664ms 3.328ms 852ms 90% of range 6ms 12ms 24.1ms 6.18s
... (time doubles with every step)
ALC attack (gain ramp-down) time (ALCMODE == 1) Per step 0000 0001 0010 1010 22.7us 45.4us 90.8us 23.2ms Per 6dB 182.4us 363.2us 726.4us 186ms 90% of range 1.31ms 2.62ms 5.26ms 1.348s
... (time doubles with every step) Table 20 ALC Control Registers When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the INPPGAVOLL/R register bits.
MINIMUM AND MAXIMUM GAIN
The MINGAIN and MAXGAIN register sets the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled.
PEAK LIMITER
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (-1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.
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NOISE GATE
When the signal is very quiet and consists mainly of noise, the ALC function may cause "noise pumping", i.e. loud hissing noise during silence periods. The WM8980 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, NGTH. The noise gate cuts in when: Signal level at ADC [dBFS] < NGTH [dBFS] + PGA gain [dB] + Mic Boost gain [dB] This is equivalent to: Signal level at input pin [dBFS] < NGTH [dBFS] The PGA gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set-up of the function. The noise gate only operates in conjunction with the ALC and cannot be used in limiter mode. REGISTER ADDRESS R35 ALC Noise Gate Control BIT 2:0 LABEL NGTH DEFAULT 000 DESCRIPTION Noise gate threshold: 000=-39dB 001=-45dB 010=-51db ... (6dB steps) 111=-81dB Noise gate function enable 1 = enable 0 = disable
3
NGEN
0
Table 21 ALC Noise Gate Control
OUTPUT SIGNAL PATH
The WM8980 output signal paths consist of digital application filters, up-sampling filters, stereo Hi-Fi DACs, analogue mixers, speaker, stereo headphone and stereo line/mono/midrail output drivers. The digital filters and DAC are enabled by register bits DACENL And DACENR. The mixers and output drivers can be separately enabled by individual control bits (see Analogue Outputs). Thus it is possible to utilise the analogue mixing and amplification provided by the WM8980, irrespective of whether the DACs are enabled or not. The WM8980 DACs receive digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions: Digital volume control Graphic equaliser Digital peak limiter. Sigma-Delta Modulation High performance sigma-delta 24-bit audio DAC converts the digital data into an analogue signal.
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Figure 21 DAC Digital Filter Path The analogue outputs from the DACs can then be mixed with the aux analogue inputs and the ADC analogue inputs. The mix is fed to the output drivers for headphone (LOUT1/ROUT1), speaker (LOUT2/ROUT2) or line (OUT3/OUT4). OUT3 and OUT4 have additional mixers which allow them to output different signals to the headphone and speaker outputs.
DIGITAL PLAYBACK (DAC) PATH
Digital data is passed to the WM8980 via the flexible audio interface and is then passed through a variety of advanced digital filters (as shown in Figure 21) to the hi-fi DACs. The DACs are enabled by the DACENL/R register bits. REGISTER ADDRESS R3 Power Management 3 BIT 0 LABEL DACENL DEFAULT 0 DESCRIPTION Left channel DAC enable 0 = DAC disabled 1 = DAC enabled Right channel DAC enable 0 = DAC disabled 1 = DAC enabled
1
DACENR
0
Table 22 DAC Enable Control The WM8980 also has a Soft Mute function, which, when enabled, gradually attenuates the volume of the digital signal to zero. When disabled, the gain will ramp back up to the digital gain setting. This function is enabled by default. To play back an audio signal, this function must first be disabled by setting the SOFTMUTE bit to zero. REGISTER ADDRESS R10 DAC Control BIT 0 LABEL DACPOLL DEFAULT 0 DESCRIPTION Left DAC output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) Right DAC output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) Automute enable 0 = Amute disabled 1 = Amute enabled DAC oversampling rate select: 0=64x (lowest power) 1=128x (best SNR) Softmute enable: 0=Enabled 1=Disabled
1
DACPOLR
0
2
AMUTE
0
3
DACOSR128
0
6
SOFTMUTE
0
Table 23 DAC Control Register The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters the multi-bit, sigma-delta DACs, which convert it to a high quality analogue audio signal. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low distortion.
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Pre-Production The DAC output phase defaults to non-inverted. Setting DACPOLL will invert the DAC output phase on the left channel and DACPOLR inverts the phase on the right channel.
AUTO-MUTE
The DAC has an auto-mute function which applies an analogue mute when 1024 consecutive zeros are detected. The mute is released as soon as a non-zero sample is detected. Automute can be disabled using the AMUTE control bit.
DIGITAL HI-FI DAC VOLUME (GAIN) CONTROL
The signal volume from each Hi-Fi DAC can be controlled digitally. The gain and attenuation range is -127dB to 0dB in 0.5dB steps. The level of attenuation for an eight-bit code X is given by: 0.5 x (X-255) dB for 1 X 255; REGISTER ADDRESS R11 Left DAC Digital Volume BIT 7:0 LABEL DACVOLL [7:0] MUTE for X = 0 DEFAULT 11111111 ( 0dB ) DESCRIPTION Left DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB DAC left and DAC right volume do not update until a 1 is written to DACVU (in reg 11 or 12) Right DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB DAC left and DAC right volume do not update until a 1 is written to DACVU (in reg 11 or 12)
8
DACVU
Not latched 11111111 ( 0dB )
R12 Right DAC Digital Volume
7:0
DACVOLR [7:0]
8
DACVU
Not latched
Table 24 DAC Digital Volume Control Note: An additional gain of up to +12dB can be added using the gain block embedded in the digital peak limiter circuit (see DAC OUTPUT LIMITER section).
5-BAND EQUALISER
A 5-band graphic equaliser function which can be used to change the output frequency levels to suit the environment. This can be applied to the ADC or DAC path and is described in the 5-BAND EQUALISER section for further details on this feature.
3-D ENHANCEMENT
The WM8980 has an advanced digital 3-D enhancement feature which can be used to vary the perceived stereo separation of the left and right channels. Like the 5-band equaliser this feature can be applied to either the ADC record path or the DAC playback path but not both simultaneously. See the 3-D STEREO ENHANCEMENT section for further details on this feature.
DAC DIGITAL OUTPUT LIMITER
The WM8980 has a digital output limiter function. The operation of this is shown in Figure 22. In this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic.
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Figure 22 DAC Digital Limiter Operation The limiter has a programmable upper threshold which is close to 0dB. Referring to Figure 22, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter. Signals above the upper threshold are attenuated at a specific attack rate (set by the LIMATK register bits) until the signal falls below the threshold. The limiter also has a lower threshold 1dB below the upper threshold. When the signal falls below the lower threshold the signal is amplified at a specific decay rate (controlled by LIMDCY register bits) until a gain of 0dB is reached. Both threshold levels are controlled by the LIMLVL register bits. The upper threshold is 0.5dB above the value programmed by LIMLVL and the lower threshold is 0.5dB below the LIMLVL value.
VOLUME BOOST
The limiter has programmable upper gain which boosts signals below the threshold to compress the dynamic range of the signal and increase its perceived loudness. This operates as an ALC function with limited boost capability. The volume boost is from 0dB to +12dB in 1dB steps, controlled by the LIMBOOST register bits. The output limiter volume boost can also be used as a stand alone digital gain boost when the limiter is disabled.
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REGISTER ADDRESS R24 DAC digital limiter control 1 BIT 3:0 LABEL LIMATK DEFAULT 0010
Pre-Production
DESCRIPTION Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale proportionally with sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms
7:4
LIMDCY
0011
Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale proportionally with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms 0111=96ms 1000=192ms 1001=384ms 1010=768ms 1011 to 1111=1.536s
8
LIMEN
0
Enable the DAC digital limiter: 0=disabled 1=enabled Limiter volume boost (can be used as a stand alone volume boost when LIMEN=0): 0000=0dB 0001=+1dB 0010=+2dB ... (1dB steps) 1011=+11dB 1100=+12dB 1101 to 1111=reserved
R25 DAC digital limiter control 2
3:0
LIMBOOST
0000
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Programmable signal threshold level (determines level at which the limiter starts to operate) 000=-1dB 001=-2dB 010=-3dB 011=-4dB 100=-5dB 101 to 111=-6dB Table 25 DAC Digital Limiter Control
5-BAND GRAPHIC EQUALISER
A 5-band graphic equaliser (EQ) is provided, which can be applied to the ADC or DAC path, together with 3D enhancement, under control of the EQ3DMODE register bit. REGISTER ADDRESS R18 EQ Control 1 BIT 8 LABEL EQ3DMODE DEFAULT 1 DESCRIPTION 0 = Equaliser and 3D Enhancement applied to ADC path 1 = Equaliser and 3D Enhancement applied to DAC path
Table 26 EQ and 3D Enhancement DAC or ADC Path Select
The equaliser consists of low and high frequency shelving filters (Band 1 and 5) and three peak filters for the centre bands. Each has adjustable cut-off or centre frequency, and selectable boost (+/- 12dB in 1dB steps). The peak filters have selectable bandwidth.
REGISTER ADDRESS R18 EQ Band 1 Control
BIT 4:0 6:5
LABEL EQ1G EQ1C
DEFAULT 01100 (0dB) 01
DESCRIPTION Band 1 Gain Control. See Table 32 for details. Band 1 Cut-off Frequency: 00=80Hz 01=105Hz 10=135Hz 11=175Hz
Table 27 EQ Band 1 Control
REGISTER ADDRESS R19 EQ Band 2 Control
BIT 4:0 6:5
LABEL EQ2G EQ2C
DEFAULT 01100 (0dB) 01
DESCRIPTION Band 2 Gain Control. See Table 32 for details. Band 2 Centre Frequency: 00=230Hz 01=300Hz 10=385Hz 11=500Hz Band 2 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth
8
EQ2BW
0
Table 28 EQ Band 2 Control
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REGISTER ADDRESS R20 EQ Band 3 Control BIT 4:0 6:5 LABEL EQ3G EQ3C DEFAULT 01100 (0dB) 01
Pre-Production
DESCRIPTION Band 3 Gain Control. See Table 32 for details. Band 3 Centre Frequency: 00=650Hz 01=850Hz 10=1.1kHz 11=1.4kHz Band 3 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth
8
EQ3BW
0
Table 29 EQ Band 3 Control
REGISTER ADDRESS R21 EQ Band 4 Control
BIT 4:0 6:5
LABEL EQ4G EQ4C
DEFAULT 01100 (0dB) 01
DESCRIPTION Band 4 Gain Control. See Table 32 for details Band 4 Centre Frequency: 00=1.8kHz 01=2.4kHz 10=3.2kHz 11=4.1kHz Band 4 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth
8
EQ4BW
0
Table 30 EQ Band 4 Control
REGISTER ADDRESS R22 EQ Band 5 Gain Control
BIT 4:0 6:5
LABEL EQ5G EQ5C
DEFAULT 01100 (0dB) 01
DESCRIPTION Band 5 Gain Control. See Table 32 for details. Band 5 Cut-off Frequency: 00=5.3kHz 01=6.9kHz 10=9kHz 11=11.7kHz
Table 31 EQ Band 5 Control
GAIN REGISTER 00000 00001 00010 .... (1dB steps) 01100 01101 11000 11001 to 11111 Table 32 Gain Register Table
GAIN +12dB +11dB +10dB 0dB -1dB -12dB Reserved
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The WM8980 has a digital 3D enhancement option to increase the perceived separation between the left and right channels. Selection of 3D for record or playback is controlled by register bit EQ3DMODE. Switching this bit from record to playback or from playback to record may only be done when ADC and DAC are disabled. The WM8980 control interface will only allow EQ3DMODE to be changed when ADC and DAC are disabled (ie ADCENL = 0, ADCENR = 0, DACENL = 0 and DACENR = 0). The DEPTH3D setting controls the degree of stereo expansion. When 3D enhancement is used, it may be necessary to attenuate the signal by 6dB to avoid limiting.
3D STEREO ENHANCEMENT
REGISTER ADDRESS R41 (29h) 3D
BIT 3:0
LABEL DEPTH3D[3:0]
DEFAULT 0000
DESCRIPTION Stereo depth 0000: 0% (minimum 3D effect) 0001: 6.67% .... 1110: 93.3% 1111: 100% (maximum 3D effect)
Table 33 3D Stereo Enhancement Function
ANALOGUE OUTPUTS
The WM8980 has three sets of stereo analogue outputs. These are: * * * LOUT1 and ROUT1 which are normally used to drive a headphone load. LOUT2 and ROUT2 - normally used to drive an 8 BTL speaker. OUT3 and OUT4 - can be configured as a stereo line out (OUT3 is left output and OUT4 is right output). OUT4 can also be used to provide a mono mix of left and right channels.
LOUT2, ROUT2, OUT3 and OUT4 are supplied from SPKVDD and are capable of driving up to 1.5Vrms signals as shown in Figure 23. LOUT1 and ROUT1 are supplied from AVDD and can only drive out a 1V rms signal (AVDD/3.3). LOUT1, ROUT1, LOUT2 and ROUT2 have individual analogue volume PGAs with -57dB to +6dB ranges. There are four output mixers in the output signal path, the left and right channel mixers which control the signals to speaker, headphone (and optionally the line outputs) and also dedicated OUT3 and OUT4 mixers.
LEFT AND RIGHT OUTPUT CHANNEL MIXERS
The left and right output channel mixers are shown in Figure 23. These mixers allow the AUX inputs, the ADC bypass and the DAC left and right channels to be combined as desired. This allows a mono mix of the DAC channels to be done as well as mixing in external line-in from the AUX or speech from the input bypass path. The AUX and bypass inputs have individual volume control from -15dB to +6dB and the DAC volume can be adjusted in the digital domain if required. The output of these mixers is connected to both the headphone (LOUT1 and ROUT1) and speaker (LOUT2 and ROUT2) and can optionally be connected to the OUT3 and OUT4 mixers.
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Figure 23 Left/Right Output Channel Mixers
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REGISTER ADDRESS R49 Output mixer control BIT 5 LABEL DACR2LMIX DEFAULT 0 DESCRIPTION Right DAC output to left output mixer 0 = not selected 1 = selected Left DAC output to right output mixer 0 = not selected 1 = selected Left DAC output to left output mixer 0 = not selected 1 = selected Left bypass path (from the left channel input boost output) to left output mixer 0 = not selected 1 = selected Left bypass volume contol to output channel mixer: 000 = -15dB 001 = -12dB ... 101 = 0dB 110 = +3dB 111 = +6dB Left Auxilliary input to left channel output mixer: 0 = not selected 1 = selected Aux left channel input to left mixer volume control: 000 = -15dB 001 = -12dB ... 101 = 0dB 110 = +3dB 111 = +6dB
6
DACL2RMIX
0
R50 Left channel output mixer control
0
DACL2LMIX
1
1
BYPL2LMIX
0
4:2
BYPLMIXVOL
000
5
AUXL2LMIX
0
8:6
AUXLMIXVOL
000
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R51 Right channel output mixer control 0 DACR2RMIX 1
Pre-Production Right DAC output to right output mixer 0 = not selected 1 = selected Right bypass path (from the right channel input boost output) to right output mixer 0 = not selected 1 = selected Right bypass volume control to output channel mixer: 000 = -15dB 001 = -12dB ... 101 = 0dB 110 = +3dB 111 = +6dB Right Auxiliary input to right channel output mixer: 0 = not selected 1 = selected Aux right channel input to right mixer volume control: 000 = -15dB 001 = -12dB ... 101 = 0dB 110 = +3dB 111 = +6dB Left output channel mixer enable: 0 = disabled 1= enabled Right output channel mixer enable: 0 = disabled 1 = enabled
1
BYPR2RMIX
0
4:2
BYPRMIXVOL
000
5
AUXR2RMIX
0
8:6
AUXRMIXVOL
000
R3 Power management 3
2
LMIXEN
0
3
RMIXEN
0
Table 34 Left and Right Output Mixer Control
HEADPHONE OUTPUTS (LOUT1 AND ROUT1)
The headphone outputs, LOUT1 and ROUT1 can drive a 16 or 32 headphone load, either through DC blocking capacitors, or DC coupled without any capacitor. Each headphone output has an analogue volume control PGA with a gain range of -57dB to +6dB as shown in Figure 26.
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Figure 24 Headphone Outputs LOUT1 and ROUT1
REGISTER ADDRESS R52 LOUT1 Volume control
BIT 7
LABEL LOUT1ZC
DEFAULT 0
DESCRIPTION Headphone volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Left headphone output mute: 0 = Normal operation 1 = Mute Left headphone output volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB LOUT1 and ROUT1 volumes do not update until a 1 is written to HPVU (in reg 52 or 53) Headphone volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Right headphone output mute: 0 = Normal operation 1 = Mute Right headphone output volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB LOUT1 and ROUT1 volumes do not update until a 1 is written to HPVU (in reg 52 or 53)
6
LOUT1MUTE
0
5:0
LOUT1VOL
111001
8
HPVU
Not latched
R53 ROUT1 Volume control
7
ROUT1ZC
0
6
ROUT1MUTE
0
5:0
ROUT1VOL
111001
8
HPVU
Not latched
Table 35 OUT1 Volume Control
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Headphone Output using DC Blocking Capacitors:
DC Coupled Headphone Output:
Figure 25 Recommended Headphone Output Configurations When DC blocking capacitors are used, then their capacitance and the load resistance together determine the lower cut-off frequency, fc. Increasing the capacitance lowers fc, improving the bass response. Smaller capacitance values will diminish the bass response. Assuming a 16 load and C1, C2 = 220F: fc = 1 / 2 RLC1 = 1 / (2 x 16 x 220F) = 45 Hz In the DC coupled configuration, the headphone "ground" is connected to the VMID pin. The OUT3/4 pins can be configured as a DC output driver by setting the OUT3MUTE and OUT4MUTE register bit. The DC voltage on VMID in this configuration is equal to the DC offset on the LOUT1 and ROUT1 pins therefore no DC blocking capacitors are required. This saves space and material cost in portable applications. Note that OUT3 and OUT4 have an optional output boost of 1.5x. When these are configured in this output boost mode (OUT3BOOST/OUT4BOOST=1) then the VMID value of these outputs will be equal to 1.5xAVDD/2 and will not match the VMID of the headphone drivers. Do not use the DC coupled output mode in this configuration. It is recommended to connect the DC coupled outputs only to headphones, and not to the line input of another device. Although the built-in short circuit protection will prevent any damage to the headphone outputs, such a connection may be noisy, and may not function properly if the other device is grounded.
SPEAKER OUTPUTS (LOUT2 AND ROUT2)
The outputs LOUT2 and ROUT2 are designed to drive an 8 BTL speaker but can optionally drive two headphone loads of 16/32 or a line output (see Headphone Output and Line Output sections, respectively). Each output has an individual volume control PGA, an output boost/level shift bit, a mute and an enable as shown in Figure 26. LOUT2 and ROUT2 output the left and right channel mixer outputs respectively. The ROUT2 signal path also has an optional invert. The amplifier used for this invert can be used to mix in the AUXR signal with an adjustable gain range of -15dB -> +6dB. This allows a `beep' signal to be applied only to the speaker output without affecting the HP or line outputs.
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Figure 26 Speaker Outputs LOUT2 and ROUT2
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REGISTER ADDRESS R54 LOUT2 (SPK) Volume control BIT 7 LABEL LOUT2ZC DEFAULT 0
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DESCRIPTION Speaker volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Left speaker output mute: 0 = Normal operation 1 = Mute Left speaker output volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB LOUT2 and ROUT2 volumes do not update until a 1 is written to SPKVU (in reg 54 or 55) Speaker volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Right speaker output mute: 0 = Normal operation 1 = Mute Right speaker output volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB LOUT2 and ROUT2 volumes do not update until a 1 is written to SPKVU (in reg 54 or 55)
6
LOUT2MUTE
0
5:0
LOUT2VOL
111001
8
SPKVU
Not latched
R55 ROUT2 (SPK) Volume control
7
ROUT2ZC
0
6
ROUT2MUTE
0
5:0
ROUT2VOL
111001
8
SPKVU
Not latched
Table 36 Speaker Volume Control The signal output on LOUT2/ROUT2 comes from the Left/Right Mixer circuits and can be any combination of the DAC output, the Bypass path (output of the input boost stage) and the AUX input. The LOUT2/ROUT2 volume is controlled by the LOUT2VOL/ ROUT2VOL register bits. Gains over 0dB may cause clipping if the signal is large. The LOUT2MUTE/ ROUT2MUTE register bits cause the speaker outputs to be muted (the output DC level is driven out). The output pins remain at the same DC level (DCOP), so that no click noise is produced when muting or un-muting The speaker output stages also have a selectable gain boost of 1.5x (3.52dB). When this boost is enabled the output DC level is also level shifted (from AVDD/2 to 1.5xAVDD/2) to prevent the signal from clipping. A dedicated amplifier BUFDCOP, as shown in Figure 27, is used to perform the DC level shift operation. This buffer must be enabled using the BUFDCOPEN register bit for this operating mode. It should also be noted that if SPKVDD is not equal to or greater than 1.5xAVDD this boost mode may result in signals clipping. Table 38 summarises the effect of the SPKBOOST control bits.
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REGISTER ADDRESS R49 Output control BIT 2 LABEL SPKBOOST DEFAULT 0 DESCRIPTION 0 = speaker gain = -1; DC = AVDD / 2 1 = speaker gain = +1.5; DC = 1.5 x AVDD / 2 Dedicated buffer for DC level shifting output stages when in 1.5x gain boost configuration. 0=Buffer disabled 1=Buffer enabled (required for 1.5x gain boost)
R1 Power management 1
8
BUFDCOPEN
0
Table 37 Speaker Boost Stage Control SPKBOOST 0 1 OUTPUT STAGE GAIN 1x (0dB) 1.5x (3.52dB) OUTPUT DC LEVEL AVDD/2 1.5xAVDD/2 OUTPUT STAGE CONFIGURATION Inverting Non-inverting
Table 38 Output Boost Stage Details
REGISTER ADDRESS R43 Beep control
BIT 5 4 3:1
LABEL MUTERPGA2INV INVROUT2 BEEPVOL
DEFAULT 0 0 000
DESCRIPTION Mute input to INVROUT2 mixer Invert ROUT2 output AUXR input to ROUT2 inverter gain 000 = -15dB ... 111 = +6dB 0 = mute AUXR beep input 1 = enable AUXR beep input
0
BEEPEN
0
Table 39 AUXR - ROUT2 BEEP Mixer Function
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ZERO CROSS TIMEOUT
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A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. This is enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital and is equal to 221 * input clock period. REGISTER ADDRESS R7 Additional Control BIT 0 LABEL SLOWCLKEN 0 DEFAULT DESCRIPTION Slow clock enable. Used for both the jack insert detect debounce circuit and the zero cross timeout. 0 = slow clock disabled 1 = slow clock enabled
Table 40 Timeout Clock Enable Control
OUT3/OUT4 MIXERS AND OUTPUT STAGES
The OUT3/OUT4 pins can provide an additional stereo line output, a mono output, or a pseudo ground connection for headphones. There is a dedicated analogue mixer for OUT3 and one for OUT4 as shown in Figure 28. The OUT3 and OUT4 output stages are powered from SPKVDD and SPKGND. The individually controllable outputs also incorporate an optional 1.5x boost and level shifting stage.
Figure 28 OUT3 and OUT4 Mixers
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OUT4 can provide a buffered midrail headphone pseudo-ground, a right line output, or a mono mix output.
REGISTER ADDRESS R56 OUT3 mixer control
BIT 6
LABEL OUT3MUTE
DEFAULT 0
DESCRIPTION 0 = Output stage outputs OUT3 mixer 1 = Output stage muted - drives out VMID. Can be used as VMID buffer in this mode. OUT4 mixer output to OUT3 0 = disabled 1= enabled Left ADC input to OUT3 0 = disabled 1= enabled Left DAC mixer to OUT3 0 = disabled 1= enabled Left DAC output to OUT3 0 = disabled 1= enabled 0 = Output stage outputs OUT4 mixer 1 = Output stage muted - drives out VMID. Can be used as VMID buffer in this mode. 0=OUT4 normal output 1=OUT4 attenuated by 6dB Left DAC mixer to OUT4 0 = disabled 1= enabled Left DAC to OUT4 0 = disabled 1= enabled Right ADC input to OUT4 0 = disabled 1= enabled Right DAC mixer to OUT4 0 = disabled 1= enabled Right DAC output to OUT4 0 = disabled 1= enabled
3
OUT4_2OUT3
0
2
BYPL2OUT3
0
1
LMIX2OUT3
0
0
LDAC2OUT3
1
R57 OUT4 mixer control
6
OUT4MUTE
0
5 4
HALFSIG LMIX2OUT4
0 0
3
LDAC2OUT4
0
2
BYPR2OUT4
0
1
RMIX2OUT4
0
0
RDAC2OUT4
1
Table 41 OUT3/OUT4 Mixer Registers The OUT3 and OUT4 output stages each have a selectable gain boost of 1.5x (3.52dB). When this boost is enabled the output DC level is also level shifted (from AVDD/2 to 1.5xAVDD/2) to prevent the signal from clipping. A dedicated amplifier BUFDCOP, as shown in Figure 29, is used to perform the DC level shift operation. This buffer must be enabled using the BUFDCOPEN register bit for this operating mode. It should also be noted that if SPKVDD is not equal to or greater than 1.5xAVDD this boost mode may result in signals clipping. Table 38 summarises the effect of the OUT3BOOST and OUT4BOOST control bits.
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Figure 30 Outputs OUT3 and OUT4
REGISTER ADDRESS R49 Output control
BIT 3
LABEL OUT3BOOST
DEFAULT 0
DESCRIPTION 0 = OUT3 output gain = -1; DC = AVDD / 2 1 = OUT3 output gain = +1.5 DC = 1.5 x AVDD / 2 0 = OUT4 output gain = -1; DC = AVDD / 2 1 = OUT4 output gain = +1.5 DC = 1.5 x AVDD / 2 Dedicated buffer for DC level shifting output stages when in 1.5x gain boost configuration. 0=Buffer disabled 1=Buffer enabled (required for 1.5x gain boost)
4
OUT4BOOST
0
R1 Power management 1
8
BUFDCOPEN
0
Table 42 OUT3 and OUT4 Boost Stages Control OUT3BOOST/ OUT4BOOST 0 1 OUTPUT STAGE GAIN 1x 1.5x OUTPUT DC LEVEL AVDD/2 1.5xAVDD/2 OUTPUT STAGE CONFIGURATION Inverting Non-inverting
Table 43 OUT3/OUT4 Output Boost Stage Details
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OUTPUT PHASING
The relative phases of the analogue outputs will depend upon the following factors: 1. 2. DACPOLL and DACPOLR invert bits: Setting these bits to 1 will invert the DAC output. Mixer configuration: The polarity of the signal will depend upon the route through the mixer path. For example, DACL can be directly input to the OUT3 mixer, giving a 180 phase shift at the OUT3 mixer output. However, if DACL is input to the OUT3 mixer via the left mixer, an additional phase shift will be introduced, giving 0 phase shift at the OUT3 mixer output. Output boost set-up: When 1.5x boost is enabled on an output, no phase shift occurs. When 1.5x boost is not enabled, a 180 phase shift occurs.
3.
Figure 23 shows where these phase inversions can occur in the output signal path.
Figure 31 Output Signal Path Phasing
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Table 44 shows the polarities of the outputs in various configurations.
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Unless otherwise stated, polarity is shown with respect to left DAC output in non-inverting mode. Note that only registers relating to the mixer paths are shown here (Mixer enables, volume settings, output enables etc are not shown). CONFIGURATION MIXER PATH REGISTERS DIFFERENT FROM DEFAULT DACPOLL 0 DACPOLR INVROUT2 SPKBOOST OUT3BOOST OUT4BOOST OUT4 PHASE / MAG OUT3 PHASE / MAG LOUT1 PHASE / MAG ROUT1 PHASE / MAG LOUT2 PHASE / MAG ROUT2 PHASE / MAG 180 1
Default: Stereo DAC playback to LOUT1/ROUT1, LOUT2/ROUT2 and OUT4/OUT3 DACs inverted
0
0
0
0
0
0 1
0 1
0 1
0 1
180 1
1
1
0
0
0
0
180 1
180 1 0 1
180 1 0 1
180 1 0 1
0 1 0 1.5
0 1 0 1.5
Stereo DAC playback to LOUT1/ROUT1 and LOUT2/ROUT2 and OUT4/OUT3 (Speaker boost enabled) Stereo DAC playback to LOUT1/ROUT1 and LOUT2/ROUT2 and OUT4/OUT3 (OUT3 and OUT4 boost enabled) Stereo playback to OUT3/OUT4 (DACs input to OUT3/OUT4 mixers via left/right mixers) Differential output of right bypass path via OUT3/OUT4 (Phase shown relative to right bypass) Differential output of mono mix of DACs via LOUT2/ROUT2 (e.g. BTL speaker drive) High power speaker drive
0
0
0
1
0
0
0 1
0
0
0
0
1
1
180 1.5
180 1.5
0 1
0 1
180 1
180 1
0
0
0
0
0
0
LDAC2OUT3=0 RDAC2OUT4=0 LMIX2OUT3=1 RMIX2OUT4=1 BYPR2OUT4=1 OUT4_2OUT3=1
180 1 180 1
180 1 0 1 0 1 0 1
0 1 X
0 1 X
180 1 X
180 1 X
0
0
0
0
0
0
0
0
1
0
0
0
0 1
0 1 0 1
0 1 0 1
180 1 0 1.5
0 1 180 1.5
0
0
1
1
0
0
0 1
Table 44 Relative Output Phases Note that differential output should not be set up by combining outputs in boost mode with outputs which are not in boost mode as this would cause a DC offset current on the outputs.
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ENABLING THE OUTPUTS
Each analogue output of the WM8980 can be separately enabled or disabled. The analogue mixer associated with each output has a separate enable. All outputs are disabled by default. To save power, unused parts of the WM8980 should remain disabled. The SLEEP bit should only be set on to reduce residual device currents once all the other power management bits have been set to off. Outputs can be enabled at any time, but it is not recommended to do so when BUFIO is disabled (BUFIOEN=0) or when BUFDCOP is disabled (BUFDCOPEN=0) when configured in output boost mode, as this may cause pop noise (see "Power Management" and "Applications Information" sections). REGISTER ADDRESS R1 Power Management 1 R2 Power Management 2 R3 Power Management 3 BIT 2 6 7 8 8 7 6 LABEL BUFIOEN OUT3MIXEN OUT4MIXEN BUFDCOPEN ROUT1EN LOUT1EN SLEEP DEFAULT 0 0 0 0 0 0 0 DESCRIPTION Unused input/output tie off buffer enable OUT3 mixer enable OUT4 mixer enable Output stage 1.5xAVDD/2 driver enable ROUT1 output enable2 LOUT1 output enable2 0 = normal device operation 1 = residual current reduced in device standby mode Left mixer enable Right mixer enable Video buffer enable ROUT2 output enable2 LOUT2 output enable2 OUT3 enable
2
2 3 4 5 6 7 8
LMIXEN RMIXEN VBUFEN ROUT2EN LOUT2EN OUT3EN OUT4EN
0 0 0 0 0 0 0
OUT4 enable2
Table 45 Output Stages Power Management Control Notes: 1. 2. All "Enable" bits are 1 = ON, 0 = OFF Disabling the outputs does not automatically mute the output mixers. To avoid pop noise, it is recommended that the relevant mixer is muted before disabling outputs.Table 46
THERMAL SHUTDOWN
The speaker outputs can drive very large currents. To protect the WM8980 from overheating a thermal shutdown circuit is included. The thermal shutdown can be configured to produce an interrupt when the device reaches approximately 125oC. See General Purpose Input/Output section. REGISTER ADDRESS R49 Output control BIT 1 LABEL TSDEN DEFAULT 1 DESCRIPTION Thermal Shutdown Enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled
Table 47 Thermal Shutdown
UNUSED ANALOGUE INPUTS/OUTPUTS
Whenever an analogue input/output is disabled, it remains connected to a voltage source (either AVDD/2 or 1.5xAVDD/2 as appropriate) through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance between the voltage buffer and the output pins can be controlled using the VROI control bit. The default impedance is low, so that any capacitors on the outputs can charge up quickly at start-up. If a high impedance is desired for disabled outputs, VROI can then be set to 1, increasing the resistance to about 30k.
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REGISTER ADDRESS R49 BIT 0 LABEL VROI DEFAULT 0
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DESCRIPTION VREF (AVDD/2 or 1.5xAVDD/2) to analogue output resistance 0: approx 1k 1: approx 30 k
Table 48 Disabled Outputs to VREF Resistance A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 32. This buffer can be enabled using the BUFIOEN register bit. If the SPKBOOST, OUT3BOOST or OUT4BOOST bits are set, then the relevant outputs will be tied to the output of the DC level shift buffer at 1.5xAVDD/2 when disabled. Figure 32 summarises the tie-off options for the speaker and mono output pins.
Figure 32 Unused Input/Output Pin Tie-off Buffers
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L/ROUT2EN/ OUT3/4EN 0 0 0 0 1 1 OUT3BOOST/ OUT4BOOST/ SPKBOOST 0 0 1 1 0 1 VROI OUTPUT CONFIGURATION
0 1 0 1 X X
1k tie-off to AVDD/2 30k tie-off to AVDD/2 1k tie-off to 1.5xAVDD/2 30k tie-off to 1.5xAVDD/2 Output enabled (DC level=AVDD/2) Output enabled (DC level=1.5xAVDD/2)
Table 49 Unused Output Pin Tie-off Options
VIDEO BUFFER
DESCRIPTION
The WM8980 incorporates a current mode output video buffer capable of operating from a 2.5V supply, with an input 3rd order Low Pass Filter (LPF) and clamp. The gain through this buffer can be programmed as 0dB or 6dB (=6dB or 12dB unloaded) via the control interface. The current mode output means that the signal swing seen at the output of the buffer will be the same as that at the connection to the receiving equipment (e.g. a TV). Note that the input to the receiver should be AC coupled and terminated to 75, as is standard, for best performance.
Figure 33 Video Buffer The input clamp should be enabled when using AC coupling at the input to the video buffer, using the VBCLAMPEN register bit. Care should be taken with PCB layout, designing for at least 1GHz frequencies to avoid degrading performance. Vias and sharp corners should be avoided and parasitic capacitance minimised on signal paths, which should be kept as short and straight as possible. The VBVDD supply should be decoupled as close to the pin as possible. See the "External Components" section for more information.
LOW PASS FILTER
A low pass filter is integrated at the video buffer input, which is intended to remove images in the video DAC output waveform at multiples of the DAC clock frequency. A 3rd order Butterworth filter is used, with the following characteristics:
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WM8980 Video Buffer Filter Response
-20dBV sinewave input, 0dB gain setting, VBVDD=3.3V 10
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5
0dB 0dB Qboost 6dB 6dB Qboost
0
Amplitude (dB)
-5
-10
-15
-20
-25 10 100 1000 Frequency (kHz) 10000 100000
VIDEO BUFFER REGISTERS
Video buffer enable / disable and gain are controlled via the following registers: REGISTER ADDRESS R3 Power management 3 R40 Video Buffer 4 BIT LABEL VBUFEN DEFAULT 0 DESCRIPTION Video buffer enable 0 = disabled 1 = enabled Video buffer clamp enable 0 = disabled 1 = enabled Video buffer gain 0 = 0dB (=6dB unloaded) 1 = +6dB (=12dB unloaded) Increases the filters Q.
0
VBCLAMPEN
0
1
VBGAIN
0
4 Table 50 Video Buffer Registers
QBOOST
0
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TEST WAVEFORMS
Figure 34 Black Needle Pulse (Full frame of white with a vertical black line)
Figure 35 Dual Needle Pulse (50% grey field with closely-spaced white and black vertical lines spaced across the line scan)
Figure 36 Multiburst (A horizontal multiburst of signals with frequencies ranging from 0.5MHz to 5.75MHz)
Figure 37 White Needle Pulse (A full frame of black with a vertical white line)
CURRENT MODE OUTPUT
The current mode output employed by the WM8980 video buffer allows VBVDD to operate at lower voltages than voltage mode video buffers, reducing power consumption, while the use of a current reference resistor close to the WM8980 ensures that the signal swing seen at the output of the buffer will be the same as that at the connection to the receiving equipment (e.g. a TV), providing excellent signal reproduction. Current mode output also provides inherent short circuit protection at the signal output.
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Figure 38 Video Buffer with 0dB Gain
Figure 39 Video Buffer with 6dB Gain The outputs VBREF and VBOUT are current mirrored transistors with a 5:1 ratio, so that: iVBOUT = 5 x iVBREF. A reference resistor (187R in above examples) is used for feedback on the video buffer amplifier via the VBREF pin. The output current from VBOUT will be split between the source termination and load termination (75R each in above examples). Overall voltage gain (i.e. VBIN to TV input) is calculated as follows: VBGAIN (R40[1]) LOADED GAIN FORMULA (SOURCE AND LOAD BOTH TERMINATED WITH 75R) 5 x (RLOAD || RSOURCE) / RVBREF 10 x (RLOAD || RSOURCE) / RVBREF LOADED GAIN (VREF=187R; RSOURCE=75R; RLOAD=75R) 0dB +6dB UNLOADED GAIN (VREF=187R; RSOURCE=75R; RLOAD=0) +6dB +12dB
0 1
See applications note WAN-0166 for further information.
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The audio interface has four pins: * * * * ADCDAT: ADC data output DACDAT: DAC data input LRC: Data Left/Right alignment clock BCLK: Bit clock, for synchronisation
DIGITAL AUDIO INTERFACES
The clock signals BCLK, and LRC can be outputs when the WM8980 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Five different audio data formats are supported: * * * * * Left justified Right justified I 2S DSP mode A DSP mode B
All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8980 audio interface may be configured as either master or slave. As a master interface device the WM8980 generates BCLK and LRC and thus controls sequencing of the data transfer on ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In slave mode (MS=0), the WM8980 responds with data to clocks it receives over the digital audio interfaces.
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRC transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRC transition.
Figure 40 Left Justified Audio Interface (assuming n-bit word length)
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Pre-Production In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRC transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRC transition.
Figure 41 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following a LRC transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next.
Figure 42 I2S Audio Interface (assuming n-bit word length)
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In DSP/PCM mode, the left channel MSB is available on either the 1 (mode B) or 2nd (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
Figure 43 DSP/PCM Mode Audio Interface (mode A, LRP=0)
Figure 44 DSP/PCM Mode Audio Interface (mode B, LRP=1)
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REGISTER ADDRESS R4 Audio Interface Control BIT 0 LABEL MONO DEFAULT 0
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DESCRIPTION Selects between stereo and mono device operation: 0=Stereo device operation 1=Mono device operation. Data appears in `left' phase of LRC Controls whether ADC data appears in `right' or `left' phases of LRC clock: 0=ADC data appear in `left' phase of LRC 1=ADC data appears in `right' phase of LRC Controls whether DAC data appears in `right' or `left' phases of LRC clock: 0=DAC data appear in `left' phase of LRC 1=DAC data appears in `right' phase of LRC Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I2S format 11= DSP/PCM mode Word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits (see note) LRC clock polarity 0=normal 1=inverted BCLK polarity 0=normal 1=inverted
1
ADCLRSWAP
0
2
DACLRSWAP
0
4:3
FMT
10
6:5
WL
10
7
LRP
8
BCP
Table 51 Audio Interface Control Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected, the device will operate in 24-bit mode.
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised below. The audio interfaces can be controlled individually. Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK, and LRC are outputs. The frequency of BCLK in master mode are controlled with BCLKDIV. These are divided down versions of master clock. This may result in short BCLK pulses at the end of a LRC if there is a non-integer ratio of BCLKs to LRC clocks.
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REGISTER ADDRESS R6 Clock Generation Control BIT 0 MS LABEL DEFAULT 0 DESCRIPTION Sets the chip to be master over LRC and BCLK 0=BCLK and LRC clock are inputs 1=BCLK and LRC clock are outputs generated by the WM8980 (MASTER) Configures the BCLK output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output
4:2
BCLKDIV
000
7:5
MCLKDIV
010
8
CLKSEL
1
Table 52 Clock Control
LOOPBACK
Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data from the ADC audio interface is fed directly into the DAC data input.
COMPANDING
The WM8980 supports A-law and -law and companding and linear mode on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively.
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REGISTER ADDRESS R5 Companding Control BIT 0 LABEL LOOPBACK DEFAULT 0
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DESCRIPTION Digital loopback function 0=No loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. ADC companding 00=off (linear mode) 01=reserved 10=-law 11=A-law DAC companding 00=off (linear mode) 01=reserved 10=-law 11=A-law Companding Control 8-bit mode 0=off 1=device operates in 8-bit mode
2:1
ADC_COMP
0
4:3
DAC_COMP
0
5
WL8
0
Table 53 Companding Control Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: -law (where =255 for the U.S. and Japan): F(x) = ln( 1 + |x|) / ln( 1 + ) A-law (where A=87.6 for Europe): F(x) = A|x| / ( 1 + lnA) F(x) = ( 1 + lnA|x|) / (1 + lnA) } for x 1/A } for 1/A x 1 -1 x 1
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB's of data. Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The input data range is separated into 8 levels, allowing low amplitude signals better precision than that of high amplitude signals. This is to exploit the operation of the human auditory system, where louder sounds do not require as much resolution as quieter sounds. The companded signal is an 8bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits). Setting the WL8 register bit allows the device to operate with 8-bit data. In this mode it is possible to use 8 BCLK's per LRC frame. When using DSP mode B, this allows 8-bit data words to be output consecutively every 8 BCLK's and can be used with 8-bit data words using the A-law and u-law companding functions.
BIT7 SIGN
BIT[6:4] EXPONENT
BIT[3:0] MANTISSA
Table 54 8-bit Companded Word Composition
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u-law Companding
1 120 100 Companded Output 80 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output
Figure 45 u-Law Companding
A-law Companding
1 120 100 Companded Output 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1 Normalised Input 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output
Figure 46 A-Law Companding
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AUDIO SAMPLE RATES
Pre-Production
The WM8980 sample rates for the ADCs and the DACs are set using the SR register bits. The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these values and assume a 256fs master clock rate. If a sample rate that is not explicitly supported by the SR register settings is required then the closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack, decay and hold times will scale appropriately.
REGISTER ADDRESS R7 Additional Control
BIT 3:1
LABEL SR
DEFAULT 000
DESCRIPTION Approximate sample rate (configures the coefficients for the internal digital filters): 000=48kHz 001=32kHz 010=24kHz 011=16kHz 100=12kHz 101=8kHz 110-111=reserved
Table 55 Sample Rate Control
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
The WM8980 has an on-chip phase-locked loop (PLL) circuit that can be used to: * * Generate master clocks for the WM8980 audio functions from another external clock, e.g. in telecoms applications. Generate and output (on pin CSB/GPIO1 and/or GPI04) a clock for another part of the system that is derived from an existing audio master clock.
Figure 47 shows the PLL and internal clocking arrangment on the WM8980. The PLL can be enabled or disabled by the PLLEN register bit. Note: In order to minimise current consumption, the PLL is disabled when the VMIDSEL[1:0] bits are set to 00b. VMIDSEL[1:0] must be set to a value other than 00b to enable the PLL. REGISTER ADDRESS R1 Power management 1 BIT 5 LABEL PLLEN DEFAULT 0 PLL enable 0=PLL off 1=PLL on DESCRIPTION
Table 56 PLLEN Control Bit
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Figure 47 PLL and Clock Select Circuit The PLL frequency ratio R = f2/f1 (see Figure 47) can be set using the register bits PLLK and PLLN: PLLN = int R PLLK = int (224 (R-PLLN)) EXAMPLE: MCLK=12MHz, required clock = 12.288MHz. R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement. Enabling the divide by 2 sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz. R = 98.304 / 12 = 8.192 PLLN = int R = 8 k = int ( 224 x (8.192 - 8)) = 3221225 = 3126E9h
REGISTER ADDRESS R36 PLL N value
BIT 4 3:0
LABEL PLLPRESCALE PLLN[3:0]
DEFAULT 0 1000
DESCRIPTION Divide MCLK by 2 before input to PLL Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number).
R37 PLL K value 1 R38 PLL K Value 2 R39 PLL K Value 3
5:0
PLLK [23:18]
0Ch
8:0
PLLK [17:9]
093h
8:0
PLLK [8:0]
0E9h
Table 57 PLL Frequency Ratio Control The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings are shown in Table 58.
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MCLK (MHZ) (F1) 12 12 13 13 14.4 14.4 19.2 19.2 19.68 19.68 19.8 19.8 24 24 26 26 27 27 DESIRED OUTPUT (MHZ) 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 F2 (MHZ) 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 PRESCALE DIVIDE 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 POSTSCALE DIVIDE 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 R N (HEX) 7 8 6 7 6 6 9 A 9 9 9 9 7 8 6 7 6 7
Pre-Production K (HEX) 86C226 3126E8 F28BD4 8FD525 45A1CA D3A06E 6872AF 3D70A3 2DB492 FD809F 1F76F7 EE009E 86C226 3126E8 F28BD4 8FD525 BOAC93 482296
7.5264 8.192 6.947446 7.561846 6.272 6.826667 9.408 10.24 9.178537 9.990243 9.122909 9.929697 7.5264 8.192 6.947446 7.561846 6.690133 7.281778
Table 58 PLL Frequency Examples
GENERAL PURPOSE INPUT/OUTPUT
The WM8980 has three dual purpose input/output pins and one dedicated GPIO. * * * * CSB/GPIO1: CSB / GPIO pin L2/GPIO2: Left channel line input / headphone detection input R2/GPIO3: Right channel line input / headphone detection input GPIO4: Dedicated GPIO
The GPIO2 and GPIO3 functions are provided for use as jack detection inputs. The GPIO1 and GPIO4 functions are provided for use as jack detection inputs or general purpose outputs. The default configuration for the CSB/GPIO1 and GPIO4 pins are to be inputs. When setup as an input, the CSB/GPIO1 pin can either be used as CSB or for jack detection, depending on how the MODE pin is set. If setup as an input, the GPIO4 pin can also be used for jack detection. Table 49 illustrates the functionality of the GPIO1 and GPIO4 pins when used as general purpose outputs.
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REGISTER ADDRESS R8 GPIO Control BIT 2:0 LABEL GPIO1SEL DEFAULT 000 DESCRIPTION CSB/GPIO1 pin function select: 000= input (CSB/jack detection: depending on MODE setting) 001= reserved 010=Temp ok 011=Amute active 100=PLL clk o/p 101=PLL lock 110=logic 0 111=logic 1 GPIO1 Polarity invert 0=Non inverted 1=Inverted PLL Output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4 GPIO4 pin function select: 000= input jack detection 001= reserved 010=Temp ok 011=Amute active 100=PLL clk o/p 101=PLL lock 110=logic 0 1 IN REG MAP? 111=logic 1 0 IN REG MAP? GPIO4 Polarity invert 0=Non inverted 1=Inverted
3
GPIO1POL
0
5:4
OPCLKDIV
00
R9 GPIO Control
2:0
GPIO4SEL
000
3
GPIO4POL
0
Table 59 CSB/GPIO Control Note: If MODE is set to 3 wire mode, CSB/GPIO1 shall be used as CSB input irrespective of the GPIO1SEL[2:] bits. Note that SLOWCLKEN must be enabled when using the Jack Detect function. For further details of the Jack detect operation see the OUTPUT SWITCHING section.
OUTPUT SWITCHING (JACK DETECT)
When the device is configured with a 2-wire interface the CSB/GPIO1 pin can be used as a switch control input to automatically disable one set of outputs and enable another. The L2/GPIO2, R2/GPIO3 and GPIO4 pins can also be used for this purpose. For example, when a headphone is plugged into a jack socket then it may be desirable to disable the speaker (e.g. when one of the GPIO pins is connected to a mechanical switch in the headphone socket to detect plug-in). The GPIO pins have an internal de-bounce circuit when in this mode in order to prevent the output enables from toggling multiple times due to input glitches. This de-bounce circuit is clocked from a slow clock with period 221 x MCLK. Note that SLOWCLKEN must be enabled when using the Jack Detect function. Note that the GPIOPOL bits are not relevant for jack detection, it is the signal detected at the pin which is used.
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Pre-Production The switching on/off of the outputs is fully configurable by the user. Each output, OUT1, OUT2, OUT3 and OUT4 has 2 associated enables. OUT1_EN_0, OUT2_EN_0, OUT3_EN_0 and OUT4_EN_0 are the output enable signal which are used if the selected jack detection pin is at logic 0 (after de-bounce). OUT1_EN_1, OUT2_EN_1, OUT3_EN_1 and OUT4_EN_1 are the output enable signals which are used if the selected jack detection pin is at logic 1 (after de-bounce). Similar to the output enables, VMID, which can be driven out of OUT3 can be configured to be on/off depending on the jack detection input polarity using the VMID_EN_0 and VMID_EN_1 bits. The jack detection enables work as follows: All OUT_EN signals have an AND function performed with their normal enable signals (in Table 45). When an output is normally enabled at per Table 45, the selected jack detection enable (controlled by selected jack detection pin polarity) is set 0, it will turn the output off. If the normal enable signal is already OFF (0), the jack detection signal will have no effect due on the AND function. During jack detection if the user desires an output to be un-changed whether the jack is in or not, both the JD_EN settings i.e. JD_EN0 and JD_EN1, should be set to 0000. The VMID_EN signal has an OR function performed with the normal VMID driver enable. If the VMID_EN signal is to have no effect to normal functionality when jack detection is enabled, it should set to 0 for all JD_EN0 or JD_EN1 settings. If jack detection is not enabled (JD_EN=0), the output enables default to all 1's, allowing the outputs to be controlled as normal via the normal output enables found in Table 45. Similarly the VMID_EN signal defaults to 0 allowing the VMID driver to be controlled via the normal enable bit. REGISTER ADDRESS R9 GPIO Control BIT 5:4 LABEL JD_SEL DEFAULT 00 DESCRIPTION Pin selected as jack detection input 00 = GPIO1 01 = GPIO2 10 = GPIO3 11 = GPIO4 Jack Detection Enable 0=disabled 1=enabled [7] VMID_EN_0 [8] VMID_EN_1 Output enabled when selected jack detection input is logic 0. [0]= OUT1_EN_0 [1]= OUT2_EN_0 [2]= OUT3_EN_0 [3]= OUT4_EN_0 Output enabled when selected jack detection input is logic 1 [4]= OUT1_EN_1 [5]= OUT2_EN_1 [6]= OUT3_EN_1 [7]= OUT4_EN_1
6
JD_EN
0
8:7 R13 GPW Control 3:0
JD_VMID JD_EN0
00 0
7:4
JD_EN1
0
Table 60 Jack Detect Register Control Bits
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CONTROL INTERFACE
SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS
The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin determines the 2 or 3 wire mode as shown in Table 61. The WM8980 is controlled by writing to registers through a serial control interface. A control word consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each control register. MODE Low High INTERFACE FORMAT 2 wire 3 wire
Table 61 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on CSB/GPIO1 pin latches in a complete control word consisting of the last 16 bits.
Figure 48 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8980 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit address of each register in the WM8980). The WM8980 operates as a slave 2-wire device only. The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8980, then the WM8980 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is `1' when operating in write only mode, the WM8980 returns to the idle condition and wait for a new start condition and valid address. During a write, once the WM8980 has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8980 register address plus the first bit of register data). The WM8980 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8980 acknowledges again by pulling SDIN low. Transfers are complete when there is a low to high transition on SDIN while SCLK is high. After a complete sequence the WM8980 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
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SDIN DEVICE ADDRESS (7 BITS) RD / WR BIT ACK (LOW) CONTROL BYTE 1 (BITS 15 TO 8) ACK (LOW) CONTROL BYTE 1 (BITS 7 TO 0) ACK (LOW)
Pre-Production
SCLK START STOP
register address and 1st register data bit
remaining 8 bits of register data
Figure 49 2-Wire Serial Control Interface In 2-wire mode the WM8980 has a fixed device address, 0011010.
RESETTING THE CHIP
The WM8980 can be reset by performing a write of any value to the software reset register (address 0 hex). This will cause all register values to be reset to their default values. In addition to this there is a Power-On Reset (POR) circuit which ensures that the registers are set to default when the device is powered up.
POWER SUPPLIES
The WM8980 can use up to five separate power supplies: * AVDD and AGND: Analogue supply, powers all analogue functions except the speaker output and mono output drivers. AVDD can range from 2.5V to 3.6V and has the most significant impact on overall power consumption (except for power consumed in the headphone). A large AVDD slightly improves audio quality. SPKVDD and SPKGND: Headphone and Speaker supplies, power the speaker and mono output drivers. SPKVDD can range from 2.5V to 5V. SPKVDD can be tied to AVDD, but it requires separate layout and decoupling capacitors to curb harmonic distortion. With a larger SPKVDD, louder headphone and speaker outputs can be achieved with lower distortion. If SPKVDD is lower than AVDD, the output signal may be clipped. DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces. DCVDD can range from 1.71V to 3.6V, and has no effect on audio quality. The return path for DCVDD is DGND, which is shared with DBVDD. DBVDD can range from 1.71V to 3.6V. DBVDD return path is through DGND. VBVDD and VBGND: Supplies for video buffer circuit. VBVDD can range from 2.5V to 3.6V.
*
*
* *
It is possible to use the same supply voltage for all four supplies. However, digital and analogue supplies should be routed and decoupled separately on the PCB to keep digital switching noise out of the analogue signal paths. DCVDD should be greater than or equal to 1.9V when using the PLL.
RECOMMENDED POWER UP/DOWN SEQENCE
In order to minimise output `pop' and `click' noise it is recommended that the device is powered up in a controlled sequence. In addition to this it is recommended that the zero cross functions are used when changing the volume in the PGAs.
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POWER MANAGEMENT
SAVING POWER BY REDUCING OVERSAMPLING RATE
The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR and DACOSR the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device. REGISTER ADDRESS R10 DAC control R14 ADC control 3 BIT LABEL DACOSR128 DEFAULT 0 DESCRIPTION DAC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) ADC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR)
3
ADCOSR128
0
Table 62 ADC and DAC Oversampling Rate Selection
VMID
The analogue circuitry will not work when VMID is disabled (VMIDSEL[1:0] = 00b). The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the startup time of the VMID circuit.
REGISTER ADDRESS R1 Power management 1
BIT 1:0
LABEL VMIDSEL
DEFAULT 00
DESCRIPTION Reference string impedance to VMID pin (detemines startup time): 00=off (open circuit) 01=75k 10=300k 11=5k (for fastest startup)
Table 63 VMID Impedance Control
BIASEN
The analogue amplifiers will not operate unless BIASEN is enabled. REGISTER ADDRESS R1 Power management 1 BIT 3 LABEL BIASEN DEFAULT 0 DESCRIPTION Analogue amplifier bias control 0=disabled 1=enabled
Table 64 Analogue Bias Control
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ADDR B[15:9] DEC HEX 0 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 18 19 20 21 22 24 25 27 28 29 30 32 33 34 35 36 37 38 39 40 41 43 44 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0E 0F 10 12 13 14 15 16 18 19 1B 1C 1D 1E 20 21 22 23 24 25 26 27 28 29 2B 2C Software Reset Power manage't 1 Power manage't 2 Power manage't 3 Audio Interface Companding ctrl Clock Gen ctrl Additional ctrl GPIO Stuff Jack detect control DAC Control Left DAC digital Vol Right DAC dig'l Vol Jack Detect Control ADC Control Left ADC Digital Vol Right ADC Digital Vol EQ1 - low shelf EQ2 - peak 1 EQ3 - peak 2 EQ4 - peak 3 EQ5 - high shelf DAC Limiter 1 DAC Limiter 2 Notch Filter 1 Notch Filter 2 Notch Filter 3 Notch Filter 4 ALC control 1 ALC control 2 ALC control 3 Noise Gate PLL N PLL K 1 PLL K 2 PLL K 3 Video Buffer 3D control Beep control Input ctrl 0 0 0 MBVSEL 0 0 0 0 0 0 0 R2_2 INPPGA 0 0 MUTER PGA2INV RIN2 INPPGA 0 ALCMODE 0 0 0 0 0 0 0 0 0 PLLK[17:9] PLLK[8:0] QBOOST 0 INVROUT2 RIP2 INPPGA 0 0 0 HPFEN ADCVU ADCVU EQ3DMODE EQ2BW EQ3BW EQ4BW 0 LIMEN 0 NFU NFU NFU NFU ALCSEL 0 NFEN 0 0 0 0 ALCHLD ALCDCY 0 0 0 PLLPRE SCALE PLLK[23:18] NGEN ALCMAXGAIN 0 0 0 0 0 EQ1C EQ2C EQ3C EQ4C EQ5C LIMDCY LIMLVL NFA0[13:7] NFA0[6:0] NFA1[13:7] NFA1[6:0] ALCMINGAIN ALCLVL ALCATK NGTH PLLN[3:0] HPFAPP 0 DACVU DACVU JD_EN1 HPFCUT ADCOSR 128 ADCVOLL ADCVOLR EQ1G EQ2G EQ3G EQ4G EQ5G LIMATK LIMBOOST 0 BUFDCOP EN ROUT1EN OUT4EN BCP 0 CLKSEL 0 0 JD_VMID 0 0 0 OUT4MIX EN LOUT1EN OUT3EN LRP 0 0 MCLKDIV 0 0 JD_EN SOFT MUTE 0 0 JD_SEL 0 0 GPIO1POL GPIO4POL DACOSR 128 DACVOLL DACVOLR JD_EN0 AMUTE OPCLKDIV OUT3MIX EN SLEEP PLLEN BOOST ENR WL WL8 Software reset MICBEN BOOST ENL BIASEN INPPGA ENR RMIXEN FMT DAC_COMP BCLKDIV SR BUFIOEN INPPGA ENL LMIXEN DAC LRSWAP REGISTER NAME B8 B7 B6 B5 B4 B3 B2 B1
Pre-Production
B0
DEF'T VAL (HEX)
VMIDSEL ADCENR DACENR ADC LRSWAP 0 ADCENL DACENL MONO LOOPBACK MS SLOWCLKEN
000 000 000 050 000 140 000 000 000 000 0FF 0FF 000 100 0FF 0FF 12C 02C 02C 02C 02C 032 000 000 000 000 000 038 00B 032 000 008 00C 093 0E9
LOUT2EN ROUT2EN VBUFEN
ADC_COMP
GPIO1SEL[2:0] GPIO4SEL[2:0] DACPOLR DACPOLL
13 0D
ADCRPOL ADCLPOL
VBGAIN VBCLAMP EN DEPTH3D BEEPEN LIN2 INPPGA LIP2 INPPGA
000 000 000 033
BEEPVOL L2_2 INPPGA
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Pre-Production 45 46 47 48 49 50 51 52 53 54 55 56 57 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 Left INP PGA gain ctrl Right INP PGA gain ctrl Right ADC Boost ctrl Output ctrl Left mixer ctrl Right mixer ctrl LOUT1 (HP) volume ctrl ROUT1 (HP) volume ctrl LOUT2 (SPK) volume ctrl ROUT2 (SPK) volume ctrl OUT3 mixer ctrl OUT4 (MONO) mixer ctrl HPVU HPVU SPKVU SPKVU 0 0 INPPGA INPPGAZCL INPPGA MUTEL UPDATE INPGA INPPGAZCR INPPGA UPDATE MUTER 0 0 0 AUXLMIXVOL AUXRMIXVOL LOUT1ZC ROUT1ZC LOUT2ZC ROUT2ZC 0 0 LOUT1 MUTE ROUT1 MUTE LOUT2 MUTE ROUT2 MUTE OUT3 MUTE OUT4 MUTE 0 HALFSIG 0 LMIX2 OUT4 DACL2 RMIX L2_2BOOSTVOL R2_2BOOSTVOL DACR2 LMIX AUXL2LMIX AUXR2RMIX OUT4 BOOST PGABOOSTR 0 INPPGAVOLL INPPGAVOLR 0 0 OUT3 BOOST BYPLMIXVOL BYPRMIXVOL LOUT1VOL ROUT1VOL LOUT2VOL ROUT2VOL OUT4_ 2OUT3 LDAC2 OUT4 BYPL2 OUT3 BYPR2 OUT4 LMIX2 OUT3 RMIX2 OUT4 AUXL2BOOSTVOL AUXR2BOOSTVOL SPK BOOST TSDEN
WM8980
010 010 100 100 002 001 001 039 039 039 039 LDAC2 OUT3 RDAC2 OUT4 001 001
Left ADC Boost ctrl PGABOOSTL
VROI
BYPL2LMIX DACL2LMIX BYPR2RMIX DACR2RMIX
Table 65 WM8980 Register Map
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REGISTER BITS BY ADDRESS
Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as "Reserved" should not be changed from the default. REGISTER ADDRESS 0 (00h) 1 (01h) BIT [8:0] 8 LABEL RESET BUFDCOPEN DEFAULT N/A 0 Software reset Dedicated buffer for DC level shifting output stages when in 1.5x gain boost configuration. 0=Buffer disabled 1=Buffer enabled (required for 1.5x gain boost) OUT4 mixer enable 0=disabled 1=enabled OUT3 mixer enable 0=disabled 1=enabled PLL enable 0=PLL off 1=PLL on Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON Analogue amplifier bias control 0=disabled 1=enabled Unused input/output tie off buffer enable 0=disabled 1=enabled Reference string impedance to VMID pin 00=off (open circuit) 01=75k 10=300k 11=5k ROUT1 output enable 0=disabled 1=enabled LOUT1 output enable 0=disabled 1=enabled 0 = normal device operation 1 = residual current reduced in device standby mode Right channel Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON Left channel Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON Right channel input PGA enable 0 = disabled 1 = enabled DESCRIPTION
Pre-Production
REFER TO Resetting the Chip Analogue Outputs
7
OUT4MIXEN
0
Power Management Power Management Master Clock and Phase Locked Loop (PLL) Input Signal Path Power Management Power Management Power Management
6
OUT3MIXEN
0
5
PLLEN
0
4
MICBEN
0
3
BIASEN
0
2
BUFIOEN
0
1:0
VMIDSEL
00
2 (02h)
8
ROUT1EN
0
Power Management Power Management Power Management Power Management Power Management Power Management
7
LOUT1EN
0
6
SLEEP
0
5
BOOSTENR
0
4
BOOSTENL
0
3
INPPGAENR
0
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Pre-Production REGISTER ADDRESS 2 BIT LABEL INPPGAENL DEFAULT 0 DESCRIPTION Left channel input PGA enable 0 = disabled 1 = enabled Enable ADC right channel: 0 = ADC disabled 1 = ADC enabled Enable ADC left channel: 0 = ADC disabled 1 = ADC enabled OUT4 enable 0 = disabled 1 = enabled OUT3 enable 0 = disabled 1 = enabled LOUT2 enable 0 = disabled 1 = enabled ROUT2 enable 0 = disabled 1 = enabled Video buffer enable 0 = disabled 1 = enabled Right output channel mixer enable: 0 = disabled 1 = enabled Left output channel mixer enable: 0 = disabled 1 = enabled Right channel DAC enable 0 = DAC disabled 1 = DAC enabled Left channel DAC enable 0 = DAC disabled 1 = DAC enabled
WM8980
REFER TO Power Management Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Power Management Power Management Power Management Power Management Video Buffer
1
ADCENR
0
0
ADCENL
0
3 (03h)
8
OUT4EN
0
7
OUT3EN
0
6
LOUT2EN
0
5
ROUT2EN
0
4
VBUFEN
0
3
RMIXEN
0
Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs
2
LMIXEN
0
1
DACENR
0
0
DACENL
0
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REGISTER ADDRESS 4 (04h) 8 BIT LABEL BCP DEFAULT 0 BCLK polarity 0=normal 1=inverted LRC clock polarity 0=normal 1=inverted Word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I2S format 11= DSP/PCM mode Controls whether DAC data appears in `right' or `left' phases of LRC clock: 0=DAC data appear in `left' phase of LRC 1=DAC data appears in `right' phase of LRC Controls whether ADC data appears in `right' or `left' phases of LRC clock: 0=ADC data appear in `left' phase of LRC 1=ADC data appears in `right' phase of LRC Selects between stereo and mono device operation: 0=Stereo device operation 1=Mono device operation. Data appears in `left' phase of LRC Reserved Companding Control 8-bit mode 0=off 1=device operates in 8-bit mode DAC companding 00=off (linear mode) 01=reserved 10=-law 11=A-law ADC companding 00=off (linear mode) 01=reserved 10=-law 11=A-law Digital loopback function 0=No loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. DESCRIPTION
Pre-Production REFER TO Digital Audio Interfaces Digital Audio Interfaces Digital Audio Interfaces
7
LRP
0
6:5
WL
10
4:3
FMT
10
Digital Audio Interfaces
2
DACLRSWAP
0
Digital Audio Interfaces
1
ADCLRSWAP
0
Digital Audio Interfaces
0
MONO
0
Digital Audio Interfaces
5 (05h)
8:6 5 WL8
000 0
Digital Audio Interfaces Digital Audio Interfaces
4:3
DAC_COMP
00
2:1
ADC_COMP
00
Digital Audio Interfaces
0
LOOPBACK
0
Digital Audio Interfaces
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Pre-Production REGISTER ADDRESS 6 (06h) 8 BIT LABEL CLKSEL DEFAULT 1 DESCRIPTION Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 Configures the BCLK output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved Reserved Sets the chip to be master over LRC and BCLK 0=BCLK and LRC clock are inputs 1=BCLK and LRC clock are outputs generated by the WM8980 (MASTER) Reserved Approximate sample rate (configures the coefficients for the internal digital filters): 000=48kHz 001=32kHz 010=24kHz 011=16kHz 100=12kHz 101=8kHz 110-111=reserved Slow clock enable. Used for both the jack insert detect debounce circuit and the zero cross timeout. 0 = slow clock disabled 1 = slow clock enabled Reserved PLL Output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4 GPIO1 Polarity invert 0=Non inverted 1=Inverted
WM8980
REFER TO Digital Audio Interfaces
7:5
MCLKDIV
010
Digital Audio Interfaces
4:2
BCLKDIV
000
Digital Audio Interfaces
1 0 MS
0 0
Digital Audio Interfaces
7 (07h)
8:4 3:1 SR
00000 000
Audio Sample Rates
0
SLOWCLKEN
0
Analogue Outputs
8 (08h)
8:6 5:4 OPCLKDIV
000 00
General Purpose Input/Output (GPIO)
3
GPIO1POL
0
General Purpose Input/Output (GPIO)
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REGISTER ADDRESS BIT 2:0 LABEL GPIO1SEL [2:0] DEFAULT 000 DESCRIPTION CSB/GPIO1 pin function select: 000= input (CSB/jack detection: depending on MODE setting) 001= reserved 010=Temp ok 011=Amute active 100=PLL clk o/p 101=PLL lock 110=logic 1 111=logic 0 [7] VMID_EN_0 [8] VMID_EN_1 Jack Detection Enable 0=disabled 1=enabled Pin selected as jack detection input 00 = GPIO1 01 = GPIO2 10 = GPIO3 11 = GPIO4 GPIO4 Polarity invert 0=Non inverted 1=Inverted GPIO4 pin function select: 000= input jack detection 001= reserved 010=Temp ok 011=Amute active 100=PLL clk o/p 101=PLL lock 110=logic 1 111=logic 0 Reserved Softmute enable: 0=Disabled 1=Enabled Reserved DAC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) Automute enable 0 = Amute disabled 1 = Amute enabled Right DAC output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) Left DAC output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift)
Pre-Production REFER TO General Purpose Input/Output (GPIO)
9 (09h)
8:7
JD_VMID
00
Output Switching (Jack Detect) Output Switching (Jack Detect) Output Switching (Jack Detect)
6
JD_EN
0
5:4
JD_SEL
00
3
GPIO4POL
0
General Purpose Input/Output (GPIO) General Purpose Input/Output (GPIO)
2:0
GPIO4SEL [2:0]
000
10 (0Ah)
8:7 6 SOFTMUTE
00 0
Output Signal Path
5:4 3 DACOSR128
00 0
Power Management Output Signal Path Output Signal Path Output Signal Path
2
AMUTE
0
1
DACPOLR
0
0
DACPOLL
0
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Pre-Production REGISTER ADDRESS 11 (0Bh) 8 BIT LABEL DACVU DEFAULT N/A DESCRIPTION DAC left and DAC right volume do not update until a 1 is written to DACVU (in reg 11 or 12)
WM8980
REFER TO Digital to Analogue Converter (DAC) Digital to Analogue Converter (DAC)
7:0
DACVOLL
11111111
Left DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB DAC left and DAC right volume do not update until a 1 is written to DACVU (in reg 11 or 12) Right DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Reserved Output enabled when selected jack detection input is logic 1 [4]= OUT1_EN_1 [5]= OUT2_EN_1 [6]= OUT3_EN_1 [7]= OUT4_EN_1 Output enabled when selected jack detection input is logic 0. [0]= OUT1_EN_0 [1]= OUT2_EN_0 [2]= OUT3_EN_0 [3]= OUT4_EN_0 High Pass Filter Enable 0=disabled 1=enabled Select audio mode or application mode 0=Audio mode (1st order, fc = ~3.7Hz) 1=Application mode (2nd order, fc = HPFCUT) Application mode cut-off frequency See Table 17 for details.
12 (0Ch)
8 7:0
DACVU DACVOLR
N/A 11111111
Output Signal Path Output Signal Path
13 (0Dh)
8 7:4 JD_EN1
0 0000
Output Switching (Jack Detect)
3:0
JD_EN0
0000
Output Switching (Jack Detect)
14 (0Eh)
8
HPFEN
1
Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Power Management
7
HPFAPP
0
6:4
HPFCUT
000
3
ADCOSR 128
0
ADC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) Reserved ADC right channel polarity adjust: 0=normal 1=inverted ADC left channel polarity adjust: 0=normal 1=inverted
2 1 ADCRPOL
0 0
Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC)
0
ADCLPOL
0
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WM8980
REGISTER ADDRESS 15 (0Fh) 8 BIT LABEL ADCVU DEFAULT N/A DESCRIPTION ADC left and ADC right volume do not update until a 1 is written to ADCVU (in reg 16 or 17)
Pre-Production REFER TO Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC)
7:0
ADCVOLL
11111111
Left ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB ADC left and ADC right volume do not update until a 1 is written to ADCVU (in reg 16 or 17)
16 (10h)
8
ADCVU
N/A
Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC)
7:0
ADCVOLR
11111111
Right ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB 0 = Equaliser and 3D Enhancement applied to ADC path 1 = Equaliser and 3D Enhancement applied to DAC path Reserved EQ Band 1 Cut-off Frequency: 00=80Hz 01=105Hz 10=135Hz 11=175Hz
18 (12h)
8
EQ3DMODE
1
Output Signal Path
7 6:5 EQ1C
0
Output Signal Path
4:0 19 (13h) 8
EQ1G EQ2BW
01100 0
EQ Band 1 Gain Control. See Table 32 for details. EQ Band 2 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth Reserved EQ Band 2 Centre Frequency: 00=230Hz 01=300Hz 10=385Hz 11=500Hz
Output Signal Path Output Signal Path Output Signal Path Output Signal Path
7 6:5 EQ2C
0 01
4:0 20 (14h) 8
EQ2G EQ3BW
01100 0
EQ Band 2 Gain Control. See Table 32 for details. EQ Band 3 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth Reserved EQ Band 3 Centre Frequency: 00=650Hz 01=850Hz 10=1.1kHz 11=1.4kHz
Output Signal Path Output Signal Path Output Signal Path Output Signal Path
7 6:5 EQ3C
0 01
4:0
EQ3G
01100
EQ Band 3 Gain Control. See Table 32 for details.
Output Signal Path
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Pre-Production REGISTER ADDRESS 21 (15h) 8 BIT LABEL EQ4BW DEFAULT 0 DESCRIPTION EQ Band 4 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth Reserved EQ Band 4 Centre Frequency: 00=1.8kHz 01=2.4kHz 10=3.2kHz 11=4.1kHz 4:0 22 (16h) 8:7 6:5 EQ5C EQ4G 01100 0 01 EQ Band 4 Gain Control. See Table 32 for details. Reserved EQ Band 5 Cut-off Frequency: 00=5.3kHz 01=6.9kHz 10=9kHz 11=11.7kHz 4:0 24 (18h) 8 EQ5G LIMEN 01100 0 EQ Band 5 Gain Control. See Table 32 for details. Enable the DAC digital limiter: 0=disabled 1=enabled 7:4 LIMDCY 0011 DAC Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms 0111=96ms 1000=192ms 1001=384ms 1010=768ms 1011 to 1111=1.536s 3:0 LIMATK 0010 DAC Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms
WM8980
REFER TO Output Signal Path Output Signal Path Output Signal Path
7 6:5 EQ4C
0 01
Output Signal Path Output Signal Path Output Signal Path
Output Signal Path Output Signal Path Output Signal Path
Output Signal Path
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WM8980
REGISTER ADDRESS 25 (19h) BIT 8:7 6:4 LIMLVL LABEL DEFAULT 00 000 Reserved Programmable signal threshold level (determines level at which the DAC limiter starts to operate) 000=-1dB 001=-2dB 010=-3dB 011=-4dB 100=-5dB 101 to 111=-6dB 3:0 LIMBOOST 0000 DAC Limiter volume boost (can be used as a stand alone volume boost when LIMEN=0): 0000=0dB 0001=+1dB 0010=+2dB ... (1dB steps) 1011=+11dB 1100=+12dB 1101 to 1111=reserved 27 (1Bh) 8 NFU 0 Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Notch filter enable: 0=Disabled 1=Enabled 6:0 NFA0[13:7] 0000000 Notch Filter a0 coefficient, bits [13:7] DESCRIPTION
Pre-Production REFER TO
Output Signal Path
Output Signal Path
Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC)
7
NFEN
0
28 (1Ch)
8
NFU
0
Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Reserved Notch Filter a0 coefficient, bits [6:0]
7 6:0 NFA0[6:0]
0 0000000
29 (1Dh)
8
NFU
0
Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Reserved Notch Filter a1 coefficient, bits [13:7]
7 6:0 NFA1[13:7]
0 0000000
30 (1Eh)
8
NFU
0
Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Reserved Notch Filter a1 coefficient, bits [6:0]
7 6:0 NFA1[6:0]
0 0000000
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Pre-Production REGISTER ADDRESS 32 (20h) BIT 8:7 LABEL ALCSEL DEFAULT 00 DESCRIPTION ALC function select: 00=ALC off 01=ALC right only 10=ALC left only 11=ALC both on Reserved Set Maximum Gain of PGA 111=+35.25dB 110=+29.25dB 101=+23.25dB 100=+17.25dB 011=+11.25dB 010=+5.25dB 001=-0.75dB 000=-6.75dB Set minimum gain of PGA 000=-12dB 001=-6dB 010=0dB 011=+6dB 100=+12dB 101=+18dB 110=+24dB 111=+30dB ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ... (time doubles with every step) 1111 = 43.691s ALC target - sets signal level at ADC input 1111 : -1.5dBFS 1110 : -1.5dBFS 1101 : -3dBFS 1100 : -4.5dBFS ...... (-1.5dB steps) 0001 : -21dBFS 0000 : -22.5dBFS 34 (22h) 8 ALCMODE 0 Determines the ALC mode of operation: 0=ALC mode 1=Limiter mode Decay (gain ramp-up) time (ALCMODE ==0) Per step 0000 0001 0010 1010 or higher 0011 410us 820us 1.64ms 420ms Per 6dB 3.3ms 6.6ms 13.1ms 3.36s 90% of range 24ms 48ms 192ms 24.576s
WM8980
REFER TO Input Limiter/ Automatic Level Control (ALC)
6 5:3 ALCMAXGAIN
0 111
Input Limiter/ Automatic Level Control (ALC)
2:0
ALCMINGAIN
000
Input Limiter/ Automatic Level Control (ALC)
33 (21h)
7:4
ALCHLD
0000
Input Limiter/ Automatic Level Control (ALC)
3:0
ALCLVL
1011
Input Limiter/ Automatic Level Control (ALC)
Input Limiter/ Automatic Level Control (ALC) Input Limiter/ Automatic Level Control (ALC)
7:4
ALCDCY [3:0]
0011
... (time doubles with every step)
Decay (gain ramp-up) time (ALCMODE ==1) Per step Per 6dB 90% of range PP Rev 3.1 March 2007 95
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WM8980
REGISTER ADDRESS BIT LABEL DEFAULT 0000 0001 0010 1010 3:0 ALCATK 0010 DESCRIPTION 90.8us 181.6us 363.2us 93ms 726.4us 1.453ms 2.905ms 744ms 5.26ms 10.53ms 21.06ms 5.39s
Pre-Production REFER TO
... (time doubles with every step) ALC attack (gain ramp-down) time (ALCMODE == 0) Per step 0000 0001 0010 1010 or higher 0010 104us 208us 416us 106ms Per 6dB 832us 1.664ms 3.328ms 852ms 90% of range 6ms 12ms 24.1ms 6.18s Input Limiter/ Automatic Level Control (ALC)
... (time doubles with every step)
ALC attack (gain ramp-down) time (ALCMODE == 1) Per step 0000 0001 0010 1010 22.7us 45.4us 90.8us 23.2ms Per 6dB 182.4us 363.2us 726.4us 186ms 90% of range 1.31ms 2.62ms 5.26ms 1.348s Input Limiter/ Automatic Level Control (ALC) Input Limiter/ Automatic Level Control (ALC)
... (time doubles with every step) 35 (23h) 8:4 3 NGEN 00000 0 Reserved ALC Noise gate function enable 1 = enable 0 = disable ALC Noise gate threshold: 000=-39dB 001=-45dB 010=-51db ... (6dB steps) 111=-81dB Reserved Divide MCLK by 2 before input to PLL Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL)
2:0
NGTH
000
36 (24h)
8:5 4 PLL PRESCALE
0000 0
3:0
PLLN[3:0]
1000
Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13.
37 (25h)
8:6 5:0 PLLK[23:18]
000 01100
Reserved Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number).
38 (26h)
8:0
PLLK[17:9]
010010011
Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number).
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Pre-Production REGISTER ADDRESS 39 (27h) BIT 8:0 LABEL PLLK[8:0] DEFAULT 011101001 DESCRIPTION Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number).
WM8980
REFER TO Master Clock and Phase Locked Loop (PLL) Video Buffer Video Buffer
40 (28h)
8:2 4 1 QBOOST VBGAIN
000000 0 0
Reserved Increases `Q' of video filter Video buffer gain 0 = 0dB (=6dB unloaded) 1 = +6dB (=12dB unloaded) Video buffer clamp enable 0 = disabled 1 = enabled
0
VBCLAMPEN
0
Video Buffer
41 (29h)
8:4 3:0 DEPTH3D
00000 0000
Reserved Stereo depth 0000: 0% (minimum 3D effect) 0001: 6.67% .... 1110: 93.3% 1111: 100% (maximum 3D effect) Reserved Mute input to INVROUT2 mixer Invert ROUT2 Output AUXR input to ROUT2 inverter gain 000 = -15dB ... 111 = +6dB 0 = mute AUXR beep input 1 = enable AUXR beep input Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.6 * AVDD Reserved Connect R2 pin to right channel input PGA positive terminal. 0=R2 not connected to input PGA 1=R2 connected to input PGA amplifier positive terminal (constant input impedance). Connect RIN pin to right channel input PGA negative terminal. 0=RIN not connected to input PGA 1=RIN connected to right channel input PGA amplifier negative terminal. Connect RIP pin to right channel input PGA amplifier positive terminal. 0 = RIP not connected to input PGA 1 = right channel input PGA amplifier positive terminal connected to RIP (constant input impedance) Reserved Input Signal Path Analogue Outputs Analogue Outputs Analogue Outputs 3D Stereo Enhancement
43 (2Bh)
8:6 5 4 3:1 MUTERPGA 2INV INVROUT2 BEEPVOL
000 0 0 000
0 44 (2Ch) 8
BEEPEN MBVSEL
0 0
Analogue Outputs Input Signal Path
7 6 R2_2INP PGA
0 0
5
RIN2INP PGA
1
Input Signal Path
4
RIP2INP PGA
1
Input Signal Path
3
0
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WM8980
REGISTER ADDRESS 2 BIT LABEL L2_2INP PGA DEFAULT 0 DESCRIPTION Connect L2 pin to left channel input PGA positive terminal. 0=L2 not connected to input PGA 1=L2 connected to input PGA amplifier positive terminal (constant input impedance). Connect LIN pin to left channel input PGA negative terminal. 0=LIN not connected to input PGA 1=LIN connected to input PGA amplifier negative terminal. Connect LIP pin to left channel input PGA amplifier positive terminal. 0 = LIP not connected to input PGA 1 = input PGA amplifier positive terminal connected to LIP (constant input impedance) INPPGAVOLL and INPPGAVOLR volume do not update until a 1 is written to INPPGAUPDATE (in reg 45 or 46) Left channel input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. Mute control for left channel input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Left channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = 35.25dB INPPGAVOLL and INPPGAVOLR volume do not update until a 1 is written to INPPGAUPDATE (in reg 45 or 46) Right channel input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. Mute control for right channel input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Right channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = +35.25dB Boost enable for left channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage.
Pre-Production REFER TO Input Signal Path
1
LIN2INP PGA
1
Input Signal Path
0
LIP2INP PGA
1
Input Signal Path
45 (2Dh)
8
INPPGA UPDATE INPPGAZCL
N/A
Input Signal Path Input Signal Path
7
0
6
INPPGA MUTEL
0
Input Signal Path
5:0
INPPGA VOLL
010000
Input Signal Path
46 (2Eh)
8
INPPGA UPDATE INPPGA ZCR
N/A
Input Signal Path Input Signal Path
7
0
6
INPPGA MUTER
0
Input Signal Path
5:0
INPPGA VOLR
010000
Input Signal Path
47 (2Fh)
8
PGA BOOSTL
1
Input Signal Path
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Pre-Production REGISTER ADDRESS 7 6:4 L2_2 BOOSTVOL BIT LABEL DEFAULT 0 000 Reserved Controls the L2 pin to the left channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Reserved Controls the auxilliary amplifer to the left channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Boost enable for right channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Reserved Controls the R2 pin to the right channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Reserved Controls the auxilliary amplifer to the right channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Reserved Left DAC output to right output mixer 0 = not selected 1 = selected Right DAC output to left output mixer 0 = not selected 1 = selected 0 = OUT4 output gain = -1; DC = AVDD / 2 1 = OUT4 output gain = +1.5 DC = 1.5 x AVDD / 2 0 = OUT3 output gain = -1; DC = AVDD / 2 1 = OUT3 output gain = +1.5 DC = 1.5 x AVDD / 2 DESCRIPTION
WM8980
REFER TO
Input Signal Path
3 2:0 AUXL2 BOOSTVOL
0 000
Input Signal Path
48 (30h)
8
PGA BOOSTR
1
Input Signal Path
7 6:4 R2_2 BOOSTVOL
0 000
Input Signal Path
3 2:0 AUXR2 BOOSTVOL
0 000
Input Signal Path
49 (31h)
8:7 6 DACL2RMIX
00 0
Analogue Outputs Analogue Outputs Analogue Outputs
5
DACR2LMIX
0
4
OUT4 BOOST
0
3
OUT3 BOOST
0
Analogue Outputs
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WM8980
REGISTER ADDRESS 2 BIT LABEL SPKBOOST DEFAULT 0 DESCRIPTION 0 = speaker gain = -1; DC = AVDD / 2 1 = speaker gain = +1.5; DC = 1.5 x AVDD / 2 Thermal Shutdown Enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled VREF (AVDD/2 or 1.5xAVDD/2) to analogue output resistance 0: approx 1k 1: approx 30 k Aux left channel input to left mixer volume control: 000 = -15dB 001 = -12dB ... 101 = 0dB 110 = +3dB 111 = +6dB Left Auxilliary input to left channel output mixer: 0 = not selected 1 = selected Left bypass volume contol to output channel mixer: 000 = -15dB 001 = -12dB ... 101 = 0dB 110 = +3dB 111 = +6dB Left bypass path (from the left channel input boost output) to left output mixer 0 = not selected 1 = selected Left DAC output to left output mixer 0 = not selected 1 = selected Aux right channel input to right mixer volume control: 000 = -15dB 001 = -12dB ... 101 = 0dB 110 = +3dB 111 = +6dB Right Auxilliary input to right channel output mixer: 0 = not selected 1 = selected Right bypass volume contol to output channel mixer: 000 = -15dB 001 = -12dB ... 101 = 0dB 110 = +3dB 111 = +6dB
Pre-Production REFER TO Analogue Outputs
1
TSDEN
1
Analogue Outputs Analogue Outputs
0
VROI
0
50 (32h)
8:6
AUXLMIX VOL
000
Analogue Outputs
5
AUXL2L MIX BYPLMIX VOL
0
Analogue Outputs Analogue Outputs
4:2
000
1
BYPL2L MIX
0
Analogue Outputs
0
DACL2L MIX AUXRMIX VOL
1
Analogue Outputs Analogue Outputs
51 (33h)
8:6
000
5
AUXR2R MIX BYPRMIX VOL
0
Analogue Outputs Analogue Outputs
4:2
000
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Pre-Production REGISTER ADDRESS 1 BIT LABEL BYPR2R MIX DEFAULT 0 DESCRIPTION Right bypass path (from the right channel input boost output) to right output mixer 0 = not selected 1 = selected Right DAC output to right output mixer 0 = not selected 1 = selected LOUT1 and ROUT1 volumes do not update until a 1 is written to HPVU (in reg 52 or 53) Headphone volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Left headphone output mute: 0 = Normal operation 1 = Mute Left headphone output volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB LOUT1 and ROUT1 volumes do not update until a 1 is written to HPVU (in reg 52 or 53) Headphone volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Right headphone output mute: 0 = Normal operation 1 = Mute Right headphone output volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB LOUT2 and ROUT2 volumes do not update until a 1 is written to SPKVU (in reg 54 or 55) Speaker volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Left speaker output mute: 0 = Normal operation 1 = Mute Left speaker output volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB LOUT2 and ROUT2 volumes do not update until a 1 is written to SPKVU (in reg 54 or 55) Speaker volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately
WM8980
REFER TO Analogue Outputs
0
DACR2R MIX HPVU LOUT1ZC
1
Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs
52 (34h)
8 7
N/A 0
6
LOUT1 MUTE LOUT1VOL
0
5:0
111001
53 (35h)
8 7
HPVU ROUT1ZC
N/A 0
Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs
6
ROUT1 MUTE ROUT1VOL
0
5:0
111001
54 (36h)
8 7
SPKVU LOUT2ZC
N/A 0
Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs
6
LOUT2 MUTE LOUT2VOL
0
5:0
111001
55 (37h)
8 7
SPKVU ROUT2ZC
N/A 0
Analogue Outputs Analogue Outputs
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WM8980
REGISTER ADDRESS 6 BIT LABEL ROUT2 MUTE ROUT2VOL DEFAULT 0 DESCRIPTION Right speaker output mute: 0 = Normal operation 1 = Mute Right speaker output volume: 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB Reserved 0 = Output stage outputs OUT3 mixer 1 = Output stage muted - drives out VMID. Can be used as VMID buffer in this mode. Reserved OUT4 mixer output to OUT3 0 = disabled 1= enabled Left ADC input to OUT3 0 = disabled 1= enabled Left DAC mixer to OUT3 0 = disabled 1= enabled Left DAC output to OUT3 0 = disabled 1= enabled Reserved 0 = Output stage outputs OUT4 mixer 1 = Output stage muted - drives out VMID. Can be used as VMID buffer in this mode. 0=OUT4 normal output 1=OUT4 attenuated by 6dB Left DAC mixer to OUT4 0 = disabled 1= enabled Left DAC to OUT4 0 = disabled 1= enabled Right ADC input to OUT4 0 = disabled 1= enabled Right DAC mixer to OUT4 0 = disabled 1= enabled Right DAC output to OUT4 0 = disabled 1= enabled
Pre-Production REFER TO Analogue Outputs Analogue Outputs
5:0
111001
56 (38h)
8:7 6 OUT3MUTE
00 0
Analogue Outputs
5:4 3 OUT4_2OUT3
00 0
Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs
2
BYPL2OUT3
0
1
LMIX2OUT3
0
0
LDAC2OUT3
1
57 (39h)
8:7 6 OUT4MUTE
00 0
Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs Analogue Outputs
5 4
HALFSIG LMIX2OUT4
0 0
3
LDAC2OUT4
0
2
BYPR2OUT4
0
1
RMIX2OUT4
0
0
RDAC2OUT4
1
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Pre-Production
WM8980
DIGITAL FILTER CHARACTERISTICS
PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay ADC High Pass Filter High Pass Filter Corner Frequency -3dB -0.5dB -0.1dB DAC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay Table 66 Digital Filter Characteristics f > 0.546fs 0.546fs -55 29/fs dB +/- 0.035dB -6dB 0 0.5fs +/-0.035 dB 0.454fs 3.7 10.4 21.6 Hz f > 0.546fs 0.546fs -60 21/fs dB +/- 0.025dB -6dB 0 0.5fs +/- 0.025 dB 0.454fs TEST CONDITIONS MIN TYP MAX UNIT
TERMINOLOGY
1. 2. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple - any variation of the frequency response in the pass-band region
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WM8980
DAC FILTER RESPONSES
20 0 -20
Response (dB) 3.05 3 2.95 2.9 2.85 2.8 2.75 2.7 2.65 2.6
Pre-Production
Response (dB)
-40 -60 -80 -100 -120 -140 -160 0 0.5 1 1.5 Frequency (fs) 2 2.5
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (fs)
Figure 50 DAC Digital Filter Frequency Response (128xOSR)
20 0 -20
Figure 51 DAC Digital Filter Ripple (128xOSR)
3.05 3 2.95 2.9 2.85 2.8 2.75 2.7 2.65 2.6
Response (dB)
-60 -80 -100 -120 -140 -160 0 0.5 1 1.5 Frequency (fs) 2 2.5
Response (dB)
-40
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (fs)
Figure 52 DAC Digital Filter Frequency Response (64xOSR)
Figure 53 DAC Digital Filter Ripple (64xOSR)
ADC FILTER RESPONSES
0.2
0 -20 Response (dB)
0.15 0.1 Response (dB) 0.05 0 -0.05 -0.1 -0.15 -0.2
0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-40 -60 -80 -100 -120
0
0.1
0.2 Frequency (Fs)
0.3
0.4
0.5
Figure 54 ADC Digital Filter Frequency Response
Figure 55 ADC Digital Filter Ripple
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Pre-Production
WM8980
The WM8980 has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter is a 1st order IIR with a cut-off of around 3.7Hz. In applications mode the filter is a 2nd order high pass filter with a selectable cut-off frequency.
HIGHPASS FILTER
5 0 -5 -10 Response (dB) -15 -20 -25 -30 -35 -40 0 5 10 15 20 25 30 35 40 45 Frequency (Hz)
Figure 56 ADC Highpass Filter Response, HPFAPP=0
10 0 -10 Response (dB) -20 -30 -40
Response (dB)
10 0 -10 -20 -30 -40 -50 -60
-50 -60 0 200 400 600 Frequency (Hz) 800 1000 1200
-70 -80 0 200 400 600 Frequency (Hz) 800 1000 1200
Figure 57 ADC Highpass Filter Responses (48kHz), HPFAPP=1, all cut-off settings shown.
Figure 58 ADC Highpass Filter Responses (24kHz), HPFAPP=1, all cut-off settings shown.
10 0 -10 -20 Response (dB) -30 -40 -50 -60 -70 -80 -90 0 200 400 600 Frequency (Hz) 800 1000 1200
Figure 59 ADC Highpass Filter Responses (12kHz), HPFAPP=1, all cut-off settings shown.
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WM8980
5-BAND EQUALISER
Pre-Production
The WM8980 has a 5-band equaliser which can be applied to either the ADC path or the DAC path. The plots from Figure 60 to Figure 73 show the frequency responses of each filter with a sampling frequency of 48kHz, firstly showing the different cut-off/centre frequencies with a gain of 12dB, and secondly a sweep of the gain from -12dB to +12dB for the lowest cut-off/centre frequency of each filter.
15
15
10
10
5 Magnitude (dB)
5 Magnitude (dB)
10
0
0
0
-5
-5
-10
-10
-15 -1 10
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 60 EQ Band 1 Low Frequency Shelf Filter Cut-offs
Figure 61 EQ Band 1 Gains for Lowest Cut-off Frequency
15
15
10
10
5 Magnitude (dB)
5 Magnitude (dB)
0 1 2 3 4 5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 62 EQ Band 2 - Peak Filter Centre Frequencies, EQ2BW=0
15
Figure 63
EQ Band 2 - Peak Filter Gains for Lowest Cut-off Frequency, EQ2BW=0
10
5 Magnitude (dB)
0
-5
-10
-15 -2 10
10
-1
10
0
10 Frequency (Hz)
1
10
2
10
3
10
4
Figure 64 EQ Band 2 - EQ2BW=0, EQ2BW=1
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Pre-Production
WM8980
15
15
10
10
5 Magnitude (dB) Magnitude (dB)
0 1 2 3 4 5
5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 65 EQ Band 3 - Peak Filter Centre Frequencies, EQ3BFigure 66
EQ Band 3 - Peak Filter Gains for Lowest Cut-off Frequency, EQ3BW=0
15
10
5 Magnitude (dB)
0
-5
-10
-15 -2 10
10
-1
10
0
10 Frequency (Hz)
1
10
2
10
3
10
4
Figure 67 EQ Band 3 - EQ3BW=0, EQ3BW=1
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WM8980
Pre-Production
15
15
10
10
5 Magnitude (dB) Magnitude (dB)
0 1 2 3 4 5
5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 68 EQ Band 4 - Peak Filter Centre Frequencies, EQ3BFigure 69
EQ Band 4 - Peak Filter Gains for Lowest Cut-off Frequency, EQ4BW=0
15
10
5 Magnitude (dB)
0
-5
-10
-15 -2 10
10
-1
10
0
10 Frequency (Hz)
1
10
2
10
3
10
4
Figure 70 EQ Band 4 - EQ3BW=0, EQ3BW=1
15 15
10
10
5 Magnitude (dB) Magnitude (dB)
0 1 2 3 4 5
5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 71 EQ Band 5 High Frequency Shelf Filter Cut-offs
Figure 72 EQ Band 5 Gains for Lowest Cut-off Frequency
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Pre-Production
WM8980
Figure 73 shows the result of having the gain set on more than one channel simultaneously. The blue traces show each band (lowest cut-off/centre frequency) with 12dB gain. The red traces show the cumulative effect of all bands with +12dB gain and all bands -12dB gain, with EqxBW=0 for the peak filters.
20
15
10
Magnitude (dB)
5
0
-5
-10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 73 Cumulative Frequency Boost/Cut
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WM8980 APPLICATION INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Pre-Production
Figure 74 Recommended External Component Diagram
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Pre-Production
WM8980
PACKAGE DIAGRAM
FL: 40 PIN QFN PLASTIC PACKAGE 6 X 6 X 0.9 mm BODY, 0.50 mm LEAD PITCH
D2 31 40
DM037.B
D
DETAIL 1
30 EXPOSED GROUND 6 PADDLE
1
4
INDEX AREA (D/2 X E/2)
A
E2
E
21
10 2X 20 e 11 b 1 bbbM C A B 2X aaa C aaa C
BOTTOM VIEW
TOP VIEW
ccc C AA 5 DD
A3
A 0.08 C
7 CC BB
C
SEATING PLANE
SIDE VIEW
A1
DETAIL 2
W T A3 H b Exposed lead G
L
L1
DETAIL 1
Half etch tie bar
DETAIL 2
Symbols A A1 A3 b D D2 E E2 e G H L T W MIN 0.80 0 0.18 4.00 4.00
Dimensions (mm) NOM MAX 0.90 1.00 0.02 0.05 0.20 REF 0.25 6.00 BSC 4.15 6.00 BSC 4.15 0.50 BSC 0.213 0.1 0.40 0.1 0.2 0.30 4.25 4.25
Symbols NOTE AA BB CC DD L1 MIN 0.235 0.235 0.181 0.181 0.03
Dimensions (mm) NOM MAX NOTE 7 7 7 7 0.15
1 2 2
0.30
0.50
Tolerances of Form and Position aaa bbb ccc REF: 0.15 0.10 0.10 JEDEC, MO-220, VARIATION VJJD-2.
NOTES: 1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC, MO-220, VARIATION VJJD-2. 3. ALL DIMENSIONS ARE IN MILLIMETRES. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002. 5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. 7. DEPENDING ON THE METHOD OF LEAD TERMINATION AT THE EDGE OF THE PACKAGE, PULL BACK (L1) MAY BE PRESENT. 8. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
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WM8980
Pre-Production
IMPORTANT NOTICE
Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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